Demo Data from EDBT 2026 / reviewers in the wild / expert
Yi Wen Wong
dblp:23/7976
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
High-performance computing · 39% GPUs and heterogeneous computing · 30% Memory systems · 30% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing
GPU computing |
0.2 | 1 | 2013 | Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes · SC 2013 |
Memory systems › memory-efficient data structures
sparse matrix compression |
0.2 | 1 | 2013 | Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes · SC 2013 |
High-performance computing › sparse linear algebra › sparse matrix computation
sparse matrix-vector multiplication |
0.2 | 1 | 2013 | Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes · SC 2013 |
High-performance computing
performance optimization |
0.0 | 1 | 2013 | Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes · SC 2013 |
Methods — techniques the papers use, named apart from their topics
matrix reordering · 0.2data clustering · 0.2bit-representation-optimized compression · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Optimizing and Auto-Tuning Iterative Stencil Loops for GPUs with the In-Plane MethodabstractStencils represent an important class of computations that are used in many scientific disciplines. Increasingly, many of the stencil computations in scientific applications are being offloaded to GPUs to improve running times. Since a large part of the simulation time is spent inside the stencil kernels, optimizing the kernel is therefore important in the context of achieving greater computation efficiencies and reducing simulation time. In this work, we proposed a novel in-plane method for stencil computations on GPUs and compared its performance with the conventional method implemented in the Nvidia SDK. We also implemented an auto-tuning framework for our method to select the optimal parameters for different GPU architectures. A performance model was developed for our proposed method, and is used to speed up the auto-tuning process. Our results show that a speedup of nearly 2× can be achieved compared to Nvidia's implementation. Wai Teng Tang, Wen Jun Tan, Ratna Krishnamoorthy, Yi Wen Wong, Shyh-Hao Kuo, Rick Siow Mong Goh, Stephen John Turner, Weng-Fai Wong |
IPDPS | 4 |
| 2013 | Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemesabstractThe sparse matrix-vector (SpMV) multiplication routine is an important building block used in many iterative algorithms for solving scientific and engineering problems. One of the main challenges of SpMV is its memory-boundedness. Although compression has been proposed previously to improve SpMV performance on CPUs, its use has not been demonstrated on the GPU because of the serial nature of many compression and decompression schemes. In this paper, we introduce a family of bit-representation-optimized (BRO) compression schemes for representing sparse matrices on GPUs. The proposed schemes, BRO-ELL, BRO-COO, and BRO-HYB, perform compression on index data and help to speed up SpMV on GPUs through reduction of memory traffic. Furthermore, we formulate a BRO-aware matrix reordering scheme as a data clustering problem and use it to increase compression ratios. With the proposed schemes, experiments show that average speedups of 1.5x compared to ELLPACK and HYB can be achieved for SpMV on GPUs. Wai Teng Tang, Wen Jun Tan, Rajarshi Ray 0001, Yi Wen Wong, Weiguang Chen, Shyh-Hao Kuo, Rick Siow Mong Goh, Stephen John Turner, Weng-Fai Wong |
SC | 4 |
| 2012 | Tulipse: A Visualization Framework for User-Guided Parallelization
Yi Wen Wong, Tomasz Dubrownik, Wai Teng Tang, Wen Jun Tan, Rubing Duan, Rick Siow Mong Goh, Shyh-Hao Kuo, Stephen John Turner, Weng-Fai Wong |
Euro-Par | 1 |
| 2009 | A Tabu Search for the Heterogeneous DAG Scheduling ProblemabstractScheduling parallel applications on heterogeneous processors/architectures with different computational speed is a difficult problem. Here, a tabu search metaheuristic is developed to improve the schedule generated by list scheduling. Three neighbourhoods variants are proposed and examined, including a novel neighbourhood that takes the shape of the task graph into account. The effectiveness is evaluated based on a set of modified random benchmark graphs, including task graphs of real-world applications. Factors affecting algorithm performance are also examined. We have found that the variants proposed were able to reduce the schedule length produced by HEFT up to an average of 30% and up to on average 20% for the standard graphs. The results also show that using information about the shape of the task graph is a viable strategy. Yi Wen Wong, Rick Siow Mong Goh, Shyh-Hao Kuo, Malcolm Y. H. Low |
ICPADS | 1 |