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Gaurav Ramesh Kulkarni

dblp:23/7994 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 50% Interconnection networks and networks-on-chip · 50%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Bioinformatics and computational biology · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › network-on-chip design
application-specific noc
0.112010
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment · IEEE Trans. Computers 2010
Hardware accelerators and domain-specific architectures
bioinformatics accelerator
0.112010
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment · IEEE Trans. Computers 2010
Interconnection networks and networks-on-chip
network-on-chip design
0.112010
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment · IEEE Trans. Computers 2010
Hardware accelerators and domain-specific architectures › bioinformatics accelerator
sequence alignment accelerator
0.112010
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment · IEEE Trans. Computers 2010
Bioinformatics and computational biology
sequence alignment
0.012010
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment · IEEE Trans. Computers 2010

Methods — techniques the papers use, named apart from their topics

comparative performance and energy evaluation · 0.2
YearPublicationVenuePosition
2010 Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
abstract
The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially growing sequence databases, computing this operation at a large-scale is becoming expensive. An effective approach to speed up this operation is to integrate a very high number of processing elements in a single chip so that the massive scales of fine-grain parallelism inherent in several bioinformatics applications can be exploited efficiently. Network-on-chip (NoC) is a very efficient method to achieve such large-scale integration. In this work, we propose to bridge the gap between data generation and processing in bioinformatics applications by designing NoC architectures for the sequence alignment operation. Specifically, we 1) propose optimized NoC architectures for different sequence alignment algorithms that were originally designed for distributed memory parallel computers and 2) provide a thorough comparative evaluation of their respective performance and energy dissipation. While accelerators using other hardware architectures such as FPGA, general purpose graphics processing unit (GPU), and the cell broadband engine (CBE) have been previously designed for sequence alignment, the NoC paradigm enables integration of a much larger number of processing elements on a single chip and also offers a higher degree of flexibility in placing them along the die to suit the underlying algorithm. The results show that our NoC-based implementations can provide above 102-103-fold speedup over other hardware accelerators and above 104-fold speedup over traditional CPU architectures. This is significant because it will drastically reduce the time required to perform the millions of alignment operations that are typical in large-scale bioinformatics projects. To the best of our knowledge, this work embodies the first attempt to accelerate a bioinformatics application using NoC.
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pratim Pande, Anantharaman Kalyanaraman
IEEE Trans. Computers2