In this paper, a novel stochastic geometry-based mathematical model is constructed to examine the performance of a millimeter-wave band joint radar communication (JRC) system. The proposed system comprises two sub-systems: the sensing sub-system, in which radar detects mobile users (MUs), and the communication sub-system, in which directional antennas establish communication with the detected users. Both function-alities operate simultaneously to reduce delay and accelerate beam alignment. The system is modeled under realistic fading channel conditions with distributed scatterers and interferers. Several system parameters are considered in the analytical model, including the density of MUs and clutter from surrounding scatterers, the radar cross section (RCS) fluctuations of the target and clutter, radar search time duration, antenna directivity, and bandwidth. The results reveal that the radar sensing sub-system has the greatest impact on the overall system performance, with radar search duration being a crucial parameter for maximizing the average system throughput.

This article studies data aggregation in large-scale regularly deployed Internet of Things (IoT) networks. The data granularity, in terms of information content and temporal resolution, is parameterized by the sizes of the generated packets and the average interpacket generation time. The generated data packets at the devices are aggregated through static terrestrial gateways. Universal frequency reuse is adopted across all gateways and randomized scheduling is utilized for the IoT devices associated with each gateway. Such network model finds applications in environmental sensing, precision agriculture, and geological seismic sensing to name a few. To this end, we develop a novel spatiotemporal mathematical model to characterize the interplay between data granularity, transmission reliability, and delay. The developed model accounts for several IoT design parameters, which include packet sizes, average generation duty cycle, devices and gateways spatial densities, transmission rate adaptation, power control, and antenna directivity. For tractable analysis, we propose two accurate approximations, based on the Poisson point process (PPP), to characterize the signal-to-interference-plus-noise-ratio (SINR)-based transmission reliability. For the delay analysis, we propose a phase-type arrival/departure (PH/PH/1) queueing model that accounts for packet generation, transmission scheduling, and rate-sensitive SINR-based packet departure. The developed model is utilized to obtain the optimal transmission rate for the IoT devices that minimizes delay. The numerical results delineate the joint feasibility range of packet sizes and interarrival times for data aggregation and reveal significant gains when deploying directional antennas.

Energy harvesting from multiple sources is a more robust method for powering Internet of Things (IoT) nodes and similar wireless systems compared to harvesting from a single source. This work provides a description of an optimization CAD tool for reconfigurable capacitive DC-DC converters with multiple inputs used for energy-harvesting from multiple sources with varying levels of input power. The tool estimates the theoretical maximum efficiency for each converter configuration, along with the input power condition that achieves this performance. In addition, for given values of the available power from the harvesting sources connected to the DC-DC converter inputs, the proposed CAD tool finds the best converter configuration for that power state of the harvesters.

This paper presents a classification Convolutional Neural Network model for modulation recognition. The model is capable of classifying 11 different modulation techniques based on their In-phase and Quadrature components at baseband. The classification accuracy is higher than 80% for signals with a Signal-to-Noise Ratio higher than 2 dB. The model performance is evaluated using the same In-phase and Quadrature component data-sets used in the state of the art. Compared to previous work, the number of parameters and multiplications/additions is reduced by several orders of magnitude. The proposed Convolutional Neural Network is implemented on FPGA and achieves the same performance as the GPU model. Compared to other FPGA implementations of RF signal classifiers, the proposed implementation classifies twice as much modulation schemes while consuming only half the dynamic power.

This paper presents a low-power Bluetooth 5.1 (BT5.1) and Bluetooth Low Energy (BLE) compliant receiver (RX). The receiver has two modes of operation: a low-power mode, and a high-performance mode. It utilizes various techniques for low power consumption at both system and circuit levels. For example, it uses a Low-IF mixer-first architecture to optimize power consumption at system level. In addition, it uses harmonic down-conversion in the low-power mode to enable quadrature local oscillation generation. Circuit-level power minimization techniques include using reduced supply voltages, 500 mV for the VCOs and 700 mV for the front end, using passive mixers, and reusing the biasing currents. The proposed receiver utilizes an integrated configurable matching circuit. The proposed receiver is implemented in 65-nm CMOS technology and occupies an active area of 0.55 mm2consuming only 697 μW and 1250 μW in low- power mode and high-performance mode, respectively. The low- power RX mode achieves a noise figure of 12.82 dB and an IIP3 of +5.58 dBm. The high-performance RX mode achieves a 6.3-dB noise figure and +2.6-dBm IIP3. The proposed receiver achieves better than 65 dB image rejection.

Micro-electromechanical systems (MEMs) started to dominate the interests of the industry due to the high growth of the various radio frequency (RF) systems, such as mobile telecommunication, satellite communication and other wireless devices that accrues high frequency range. In addition to the race of miniaturizing the device feature size. However, the main obstacle of enabling such devices is that not all of the MEMS technologies are compatible with integrated circuits (IC) manufacturing process. MEMs' devices that are based on acoustics waves like surface acoustic wave (SAW) and bulk acoustic wave (BAW) overcome aforementioned limitations while providing an outstanding performance. BAW resonator is a new technology raised during the last decade which shows better temperature stability compared to SAW, better selectivity, IC manufacturing process compatibility, and lower insertion loss. Filters based on BAWs show very promising results as well. However, BAW resonators still need optimization to achieve the high-quality factor also the temperature dependency is still a big problem. A novel Thin Film bulk acoustic resonator (FBAR) design is presented in this paper using aluminum nitride (AlN) as peizoelectric material and Tungsten (W) for the electrodes, with detailed electrical model and FEM simulations using COMSOL MULTIPHYSICS. In addition, Cadence Virtuoso is used to implement and simulate the electrical model. A resonance frequency of 2.4 GHZ is achieved with quality factor (QF) of 1548 and Temperature coefficient of frequency (TCF) ∼ 4.6 (ppm/ oC).

Recently, electrical stimulation has been widely used for biomedical applications, such as cardiac pacemaker, cochlear implant, muscle exercising, vision restoration, and seizure suppression. This paper presents two compact and power-efficient optimized neural stimulators for seizure suppression. These neural stimulators compromise between various design trade-offs such as adaptability with the load variations, multi-waveform generation for different seizures suppression, power efficiency, and linearity issues. The first design is an adaptable closed-loop current stimulator with a bipolar electrode, while the other design is a multi-waveform open-loop current stimulator with a unipolar electrode. Finally, the first design optimizes the power consumption to 429.68 μW and occupies 0.11 mm2. However, the second design achieves a high-power efficiency equals 96.47 % and occupies 0.015 mm2. Both stimulators are implemented using UMC 0.13 μm CMOS technology.

Dynamic Partial Reconfiguration (DPR) proved itself for the implementation of multi-standard Software Defined Radio (SDR). Over the past few years, wireless communication standards witnessed great and rapid evolution. The market is always acquiring higher data rates and more special services. This leads to increase of design complexity, area, and power consumption. Deploying DPR technology on Field Programmable Gate Arrays (FPGAs) made it feasible to design and manufacture all wireless communications standards on the same hardware. Loading each standard on demand reduces area and power consumption. This work implements SDR transceiver system for five wireless communication standards: Bluetooth, Wi-Fi, 2G, 3G, and LTE on Zynq-7000 evaluation kit. A new partitioning approach is deployed to achieve best performance for all transceivers. The new approach proves its ability to reduce the allocated area and power consumption for all chains. Power reduction for 2G and Bluetooth is 98.43%, for 3G and Wi-Fi is 79.69%, for LTE is 50.09% compared with no DPR approach.

Internet of Things (IoT) is the ability of things to share useful data among each other. It is becoming one of the most crucial technologies of our generation, however, one of its biggest challenges is security. In this paper, a design is proposed using Advanced Encryption Standard (AES) and the Dynamic Partial Reconfiguration (DPR) feature of the FPGA to tackle the security problem. AES-128 is used with 128-bit input data and 128-bit key. DPR is a new feature that allows utilizing the same hardware for different functions, which minimizes area and power needed by a system. The variants of the DPR are one round of encryption and one round of decryption. The proposed design offers low hardware and low power consuming cryptographic algorithm. The average reduction in resources consumed is 33% for encryption and 29% for decryption and energy utilization is decreased by 43.75%. The proposed work is tested on ZC702 evaluation board, synthesized and implemented using Vivado 2015.2.

Data security is the main challenge in Internet of Things (IoT) applications. Security strength and the immunity to security attacks depend mainly on the available power budget. The power-security level trade-off is the main challenge for low power IoT applications, especially, energy limited IoT applications. In this paper, multiple encryption modes that provide different power consumption and security level values are hardware implemented. In other words, some modes provide high security levels at the expense of high power consumption and other modes provide low power consumption with low security level. Dynamic Partial Reconfiguration (DPR) is utilized to adaptively configure the hardware security module based on the available power budget. For example, for a given power constraint, the DPR controller configures the security module with the security mode that meets the available power constraint. ZC702 evaluation board is utilized to implement the proposed encryption modes using DPR. A Lightweight Authenticated Cipher (ACORN) is the most suitable encryption mode for low power IoT applications as it consumes the minimum power and area among the selected candidates at the expense of low throughput. The whole DPR system is tested with a maximum dynamic power dissipation of 10.08 mW. The suggested DPR system saves about 59.9% of the utilized LUTs compared to the individual implementation of the selected encryption modes.

Microwave photonic (MWP) processing of impulse radio ultra wideband (IR-UWB) waveforms is the most critical stage in IR-UWB over fiber (IR-UWBoF) systems with optical and/or wireless transmission. In these systems, a centralized optical processing hub is the only place where a power efficient IR-UWB signal can be generated prior to optical distribution to an optical-wireless interface. In this work, very accurate analytical expressions for the photodetected optical power of photonically generated IR-UWB waveforms are derived and maximized, considering two common types of IR-UWB waveforms. Numerical simulations show excellent agreement with the obtained analytical expressions and provide useful design insights as well as guidelines in the development of IR-UWBoF systems.

Silicon photonic-based interconnects are becoming a very promising solution for multi-core system on chip (SoC) platforms. In this paper, a novel photonic network on chip (PNoC) design for multi-core SoC is proposed, based on optical code-division multiple-access (OCDMA) using a single on/off-chip laser diode (LD). The proposed design offers a much lower optical power consumption, and consequently, cost, as compared to the state-of-the-art PNoC designs, in which multiple on/off chip LDs are usually utilized. The core-to-core communication over the proposed PNoC is simulated, with the bit error rate (BER) as the performance metric of interest. Simulation results confirm the analytical BER expressions and show that an error free core-to-core transmission is achieved.

Reconfigurability of Field Programmable Gate Array (FPGA) makes it one of the most promising approaches in the implementation of the Software Defined Radio (SDR). FPGA Dynamic Partial Reconfiguration (DPR) feature emphasizes that approach by allowing the implemented SDR system to switch between multiple communications standards in runtime reusing the same FPGA hardware resources. Reconfiguration time is a significant parameter in DPR designs especially when a fast switching is required in real time system like SDR. In this paper, different designs of Partial Reconfiguration (PR) controllers are studied and evaluated according to their impact to improve the reconfiguration time of DPR-based SDR implementation. A multi-standard convolutional encoder design is implemented using DPR with different PR controllers as a case study. The design is implemented and tested on Xilinx Zynq evaluation board “ZC702”. This comparative study provides important design insights and recommendations to the DPR-based SDR designers to help them select the best PR controller based on their system throughput requirement and power budget.

Current wireless communication devices demand multi-band/multi-standard receiver that can access all the available services specifications. This work introduces a tunable receiver front-end for multi-band multi-standard applications. The receiver adopts a down-conversion quadrature band-pass FIR charge sampling mixer tuned via its controlling clocks. A time varying impedance matching network provides further selectivity. The architecture is simulated over three different frequencies spanning two octaves (2G, 1G and 500MHz) targeting LTE specifications. The proposed design is tested across process corners and post layout. Simulations result in Noise Figure of 7.5 to 9 dB, out-of-band IIP3 of -1.9 to -7 dBm, in-band IIP3 of -1.5 to -10 dBm and S11 <;-10dB. The design is implemented using 65nm CMOS technology.

Time-Based Analog-to-Digital Converter (ADC), at scaled CMOS technology, plays a major role in designing Software Defined Radio (SDR) receivers as it manifests higher speed and lower power than conventional ADCs. Time-Based ADC includes a Voltage-to-Time converter (VTC) which converts the input voltage into a pulse delay, and a Time-to-Digital Converter which converts the pulse delay into a digital word. In this paper, a novel design of a differential VTC circuit is proposed which reports wider dynamic range and higher sensitivity than previously published VTC circuits in TSMC 65nm CMOS technology, with a supply voltage of 1.2V. This new VTC circuit operates with no sample and hold circuit for analog input frequencies up to 2.5 GHz with a linearity error of 3%.

Network-on-Chip (NoC) is an emerging solution for interconnect problems for both ASICs and FPGAs nowadays. In this paper, we deliver a comparative review between ASIC-based and FPGA-based NoCs. An exploration of design tradeoffs for different NoC design parameters is also given. We also propose an evaluation methodology and design recommendations for various design parameters for both ASIC and FPGA oriented NoCs. These design recommendations help in selecting the optimum design parameters according to the requirements of the application used.

Emerging nonvolatile universal memory technology is vital for providing the huge storage capabilities, which is needed for nanocomputing facilities. Memristor, which is recently discovered and known as the missing fourth circuit element, is a potential candidate for the next-generation memory. Memristor has received extra attention in the last few years. To support this effort, this paper presents a novel read/write circuit that facilitates the reading and writing operation of the Memristor device as a memory element. The advantages of the proposed read/write circuit are threefold. First, the proposed circuit has a nondestructive successive reading cycle capability. Second, it occupies less die area. Finally, the proposed read/write circuit offers a significant improvement in power consumption and delay time compared with other read/write circuits.

SRAM has become the dominant block in modern ICs and constitutes more than 50% of the die area. The increase of process variations with continued CMOS technology scaling is considered one of the major challenges for SRAM designers. This process variations increase causes the SRAM cells to functionally fail and reduces the chip functional yield considering the static noise margin stability failures (i.e., cell flips when accessed), write failures (i.e., cell is not written within the write window), and read access failures (i.e., incorrect read operation). In this paper, novel negative capacitance circuits are developed, for the first time, to statistically improve the SRAM read access yield under process variations by reducing the bitlines parasitic capacitance. Post layout simulation results, referring to an industrial hardware-calibrated TSMC 65-nm CMOS technology, show that the adoption of the negative capacitance circuit to a 512 SRAM cells column is capable of improving the read access yield from 61.9% to 100%.

An analog adaptive body bias (A-ABB) circuit is proposed in this paper. The A-ABB is used to compensate for die-to-die (D2D) and within-die (WID) parameter variations and accordingly, improves the circuit yield regarding the speed, the dynamic power, and the leakage power. The A-ABB consists of threshold voltage estimation circuits and analog control of the body bias performed by on-chip amplifier circuits. Circuit level simulation results of a circuit block case study, extracted from a real microprocessor critical path, referring to an industrial hardware-calibrated 65-nm CMOS technology transistor model, are demonstrated. This study shows that the proposed A-ABB reduces the standard deviations of the frequency, the dynamic power and the leakage power by factors of 6.6 X, 8.8 X, and 3.3 X, respectively, when both D2D and WID variations are considered. In addition, in this presented case study, initial total yields of 16.8% and 5.2% are improved to 99.9% and 84.1%, respectively. The advantage of the proposed A-ABB is its lower area overhead allowing it to be used at lower granularity level than that of the previously published ABB circuits.

Sub-threshold SRAM cells are attractive because of their low leakage power and low access energy. However, the susceptibility of sub-threshold SRAM cells to soft errors is high due to their low supply voltage, high density, and shrinking geometry. Moreover, the increase in statistical variations in advanced nanometer CMOS technologies poses a major challenge for sub-threshold circuits designers. In this paper, analytical models for the sub-threshold SRAM critical charge variations, which account for both die-to-die (D2D) and within-die (WID) variations, are proposed. The derived models are then compared with Monte Carlo simulations by using industrial hardware-calibrated 65-nm CMOS technology. This paper also provides novel design insights such as the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability. In addition, it demonstrates that the relative critical charge variability is minimum at a certain temperature value. Then, the circuit designer can employ these results with temperature control techniques to minimize the critical charge variability in the early design cycles, especially, for applications with strict soft error rate (SER) constraints. In Zaddition, the proposed models show that the device sub-threshold swing coefficient can be optimized to minimize the relative critical charge variability.

A direct adaptive body bias (D-ABB) circuit is proposed in this paper. The D-ABB is used to compensate for die-to-die (D2D) and within-die (WID) parameter variations, and accordingly, improves the circuit yield regarding the speed, the dynamic power, and the leakage power. The D-ABB circuit consists of threshold voltage estimation circuits and direct control of the body bias performed by on-chip direct controller circuits. Circuit level simulation results of a circuit block case study, extracted from a real microprocessor critical path, referring to an industrial hardware-calibrated 65-nm CMOS technology transistor model, are presented. These results show that the proposed D-ABB reduces the standard deviations of the frequency, the dynamic power, and the leakage power by factors of 5.5×, 6.4×, and 4.5×, respectively, when both D2D and WID variations are considered. In addition, in the presented case study, initial total yields of 16.8% and 13% are improved to 100% and 91.4%, respectively. The proposed D-ABB circuit exhibits lower area overhead compared to the other ABB circuits reported in the literature.

Nanometer SRAM cells are more susceptible to the particle strike soft errors and the increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, an analytical model for the critical charge variations accounting for both die-to-die (D2D) and within-die (WID) variations, over a wide range of bias conditions, is proposed. The derived model is verified and compared to Monte Carlo simulations by using industrial hardware-calibrated 65-nm CMOS technology. This paper shows the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability. It demonstrates that the adoption of the coupling capacitor reduces the critical charge variability. The derived analytical model accounts for the impact of the supply voltage, from 0.1 to 1.2 V, on the critical charge and its variability.

In low power synchronous systems, sub-threshold flip-flops are used to reduce the total power dissipation. Moreover, process variations create a large variability in the flip-flop power in scaled technologies impacting the power yield, especially, for sub-threshold operation. This paper presents an analysis of power yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for delay, energy, and energy-delay product (EDP) overheads to achieve this power yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has the lowest overheads while the modified clocked CMOS master slave flip-flop (M-C2MOS-MSFF) exhibits the largest overheads, and correspondingly, it is not recommended for sub-threshold operation.

Dynamic logic circuits are considered the best choice for high performance applications due to their relatively high speed. These high performance applications have strict timing constraints. Moreover, process variations create a large variability in the dynamic circuit delay in scaled technologies impacting the timing yield. In this paper, the negative capacitance is adopted, for the first time, for statistical timing yield improvement under process variations. Simulation results show that the adoption of the negative capacitance at the output of a 16-input dynamic NOR gate improves the timing yield by reducing the dynamic circuit delay. In addition, the negative capacitance adoption results in power saving of 10% and reduces the delay variability by 57.6%.