Advanced technology nodes employ a large number of innovations. In addition, they require `scaling boosters' in the design of standard-cell libraries to be able to offer the scaling benefits in area, performance, and power that we have grown accustomed to. Consequently, sub-10nm standard cells are significantly more complex than their predecessors. Cell-aware test (CAT) explicitly targets cell-internal resistive open and short defects identified through extensive characterization of the library cells. This paper is (to the best of our knowledge) the first to report on the application of CAT library characterization on a sub-10nm technology node. We used Cadence's CAT tool flow on an experimental 114-cell-library in IMEC's 3nm CMOS technology iN5. Despite the increased cell complexity, we show that the CAT flow still works, and that compared with functionally-comparable library cells in a 45nm technology, the number of potential non-equivalent defect locations, cell-level test patterns, and defect coverage did not change drastically.

This paper proposes TEASE (Technology Exploration and Analysis for SoC-level Evaluation), a framework to systematically analyze and evaluate system design in finFET-based technology node. The proposed framework combines both lithography and electrical constraints of a particular technology node to optimize the standard cell library performance. Growing complexity of logic design at nodes below 20nm causes to adopt a design style that can embrace the simplicity required to enable manufacturing, along with a process technology that can be finely tuned to the desired performance constraints. Additionally, the introduction of finFET based devices poses a new challenge for the designers to come up with an efficient standard cell template. The proposed framework can be used to detect the technology constraints that act as the bottleneck for the enablement of design at these advanced nodes. Results presented in this paper show by optimizing these bottlenecks we can improve the performance of a standard cell library significantly. Furthermore, adapting to such an analysis framework at an early stage of technology development helps to take the design constraints into the decision loop for realization of technology research into real products.

This paper presents a tool for exploring different parallelization options for an application. It can be used to quickly find a high-quality match between an application and a multi-processor platform architecture. By specifying the parallelization at a high abstraction level, and leaving the actual source code transformations to the tool, a designer can try out many parallelizations in a short time. A parallelization may use either functional or data-level splits, or a combination of both. An accompanying high-level simulator provides rapid feedback about the expected performance of a parallelization, based on platform parameters and profiling data of the sequential application on the target processor. The use of the tool and simulator are demonstrated on an MPEG-4 video encoder application and two different platform architectures.

Using software-controlled Scratch-Pad Memory (SPM) in Systems-on-Chip has the potential of reducing power consumption by using design-time application knowledge to reduce memory accesses and processor stalls. This paper presents a fully automatic application analysis and transformation tool which selects data-structures for transfer to the SPM and schedules data transfers between background memory and SPM (pre-fetching) to achieve both high performance and low power consumption. A case study applying this tool on an MPEG-4 video encoder shows an overall power reduction of 25%, a 40% power reduction in just the memories and a 40% reduction in processor cycles as compared to an optimized hardware-cache based solution.