This paper describes the world's first commercial data-driven multimedia processors (DDMPs), developed jointly by Osaka University Kochi University of Technology, and Sharp Corporation. The data-driven principle underlying the structure of these processors was realized in a super-pipelined implementation, which was in turn based on a self-timed clocking scheme. This design made it possible to realize single chip DDMPs capable of executing tens of billions of signal processing operations per second with power consumption as low as 2 W. In terms of operations per watt, the processors exhibit threefold to tenfold improvement over conventional sequential digital signal processors (DSPs). The structure of this paper is as follows: 1) a brief introduction to the data-driven processing principle; 2) a detailed description of elementary modules for the realization of self-timed pipeline microprocessors; and 3) a description of the DDMP's developed thus far in the research project, which has continued for more than a decade. Also outlined here are the numerous advantages, in terms of both function and power consumption, of the self-timed pipeline over its synchronous counterparts. Commercially available DSP-oriented asynchronous data-driven processors and their practical applications to consumer appliances such as digital TV receivers are discussed; some programming examples are provided.

Undoubtedly, users' requirements and engineering constraints will influence the future information environment. The authors have started a project named CUE (Coordinating Users' requirements and Engineering constraints). The project uses an efficient ultra-multiprocessing capability with overload tolerance and maintainability/expandability, incorporating run-time reconfiguration as essential requirements to realize distributed networking systems such as TINA, which is aimed at the interoperability, reusability and transparency of application software. To satisfy these requirements from engineering viewpoints, the CUE project proposes applying to the network systems an autonomous decentralized data-driven processor which adopts an autonomous execution control scheme in which data packets passing through the pipeline achieve all data transfer, processing and storing/buffering functions in a completely decentralized manner. The processor can therefore perform high flow-rate multimedia streams with considerable flow fluctuations and act as a functional module flexibly adding to/removing from the system at run-time without any overheads. The essential requirements to realize a distributed networking environment such as TINA are first discussed. The applicability of our data-driven processor is shown through actual performance evaluations by the latest VLSI systems. An autonomous run-time reconfiguration scheme in a multiprocessor system is proposed to demonstrate the potential of the data-driven processor. Finally, the current status and future directions of the CUE project are briefly addressed.