Architectural simulation of complex systems is usually constrained by available computational resources. Recently, several commercial parallel processing systems have appeared with price-performance levels that make very intense simulations affordable. In this paper, we briefly review architectural simulation technology, then describe the approach used to develop a parallel architectural simulator. Performance of the parallel simulator is then experimentally characterized and analyzed. This study is one of the earliest to report measured performance of a widely-used commercial simulator, running non-trivial designs on a popular parallel computing system.

The design processes are basically the same at all levels of applications - chip, board and system. Many businesses involved with design find themselves with a combination of manual methods and a variety of CA tools to accomplish different portions of this process. This implies that the information, or database, is found in a variety of media forms: on paper, on system A application B, on system C application D, etc. There is a tremendous need at this point in the CA tools industry's development to offer means by which these different parts of the design process, manual and automated, can transfer information intelligently between applications which may be resident on different platforms. Given sufficient time, and barring major differences between the various proponents, the ongoing development of industry-wide standards are possibly the solution to many of these issues.

Parallel processing is being recognized as a practical way to achieve very high performance in logic simulation of large designs. This tutorial summarizes many of the basic methods employed, and estimates attainable throughput. Next, data structuring and processing factors are explored as they impact parallel simulation. Experience indicates that support processing necessary before and after simulation kernel execution can be accelerated using parallel methods. We conclude by suggesting pitfalls to avoid, and discuss future development directions for parallel logic simulation.

The digital system design support environment at Star Technologies, Inc. has changed radically in its implementation over a few years. Nevertheless, it has remained unusually effective in meeting corporate goals. This paper summarizes this evolution and the forces that drove it. Star's projected future CAE environment is also discussed.

A new multi-layer printed circuit board routing technique is presented which combines two existing algorithms with a new cost function. The present implementation of this new technique handles up to four layers at a time. The earlier works are overviewed and enhancements incorporated in the new implementation are pointed out. Experimental results obtained using this new router on printed circuit boards of various sizes and routing densities are also described.

Classical Unconnected Set (UCS) and other iterative placement improvement algorithms may converge slowly toward desirable component arrangements. This paper discusses mechanisms that inhibit convergence, then proposes techniques for accelerating rate of improvement. A placer incorporating these procedures is described, and experimental results demonstrating effectiveness of the approach are given.

Design automation of electronic systems is generally separated into a number of distinct areas of effort. Breuer [1] has divided design automation into the areas of logic synthesis, gate simulation, partitioning, placement, routing, and fault detection and diagnosis. While this separation may not be complete or entirely accurate, these functions generally must be performed.

The concept of individualized instruction centered around a rather extensive research project has been present in education for centuries. As recently as fifty years ago many colleges and universities required some form of thesis for bachelors and masters degrees, as well as for the doctorate. However, with the pressure of increasing numbers of students the emphasis on individual study has abated to such an extent that in many schools only the PhD students have a real opportunity to engage in extensive individual work.

Several algorithms have been proposed for generating satisfactory state assignments for normal fundamental mode asynchronous sequential circuits. Programmed versions of minimal and near-minimal techniques have been incorporated in automated synthesis systems, but are known to require computational efforts which increase exponentially with flow table size. Other methods, requiring much less effort, produce assignments with far more state variables than minimal assigments.

One step in the synthesis procedure for realizing an asynchronous sequential switching circuit is the generation of next-state and output state equations from a simplified and coded flow table description of the circuit. The usual approach for determining these equations is to first construct a state table from the coded flow table, and then construct transition and output tables. For large flow tables this can be quite a lengthy procedure. This note describes an algorithm which simplifies the synthesis procedure for normal fundamental-mode circuits by permitting the determination of these equations without explicit construction of the state table, transition table, or output table. The algorithm has been programmed in PL/1.