Due to popular requests from the designers of clock and data recovery (CDR) regarding the inefficiency of generating high accuracy phase interpolator (PI), in this work, we have developed a layout generator for such circuit, different from conventional constraint-driven works. In the first stage, we propose a customized template floorplanning plus pin generation demanded by the users. In the second stage, in order to generate high accuracy layout, we implement a gridless router for signal, power supply and clock. Experiments with several configurations indicate that our approach can generate high-quality corresponding layouts that align with user expectations, and even surpass the quality of manual designs on structurally regular high-performance PIs, which are not easy and efficient to be generated by prior primitive/grid-based methods.

Separating the power delivery network (PDN) from the front-side metal stack and using the back-side metal stack primarily for the PDN has been proposed to improve the PDN performance. To well utilize the surplus routing resources left on the back side after the PDN is built, we study in this paper how to route signal nets on both front and back sides (i.e. double-sided signal routing). To this end, we present a netlist planning approach that is able to well distribute a set of signal nets to two sides and properly insert a set of bridging cells such that after performing placement legalization and signal routing on each side separately, a high-quality double-sided routing solution can be produced. Our netlist planning approach has been combined with a commercial place and route tool, and our experimental results show that compared to traditional single-sided routing without back-side PDN, double-sided routing achieves 9.1% reduction in wirelength and 1.8% decrease in via count. Additionally, for critical nets, the percentage of the total length of their wire segments routed on preferred metal layers were improved by 13.6%.

To improve the power delivery network (PDN) efficiency under the consideration of scaling trends, back-side PDN has been proposed. To well utilize the remaining routing resources on the back side after constructing the PDN, a pioneering work [4] introduced a netlist planning flow capable of distributing a set of signal nets to both sides for routing. However, it failed to consider the routing blockages of the PG network, and the overlapping regions between bounding boxes of pins assigned to the front side and back side, respectively, leading to sub-optimal wirelength. To mitigate these drawbacks, we propose a PG-aware capacity calculation to adjust the bridging cell capacities and the routing capacities for accurate back-side routing resource estimation and a bounding box-based netlist planning approach. Compared to [4], our method resulted in 2% reduction in the average wirelength and 6.4% improvement in the average timing score for the critical nets. Compared to a netlist planning method that leveraged a commercial tool, our approach reduced the average wirelength by 7.4% and improved the average timing score for the critical nets by 22.2%.

Automatic melody generation has been a long-time aspiration for both AI researchers and musicians. However, learning to generate euphonious melodies has turned out to be highly challenging. This paper introduces 1) a new variant of variational autoencoder (VAE), where the model structure is designed in a modularized manner in order to model polyphonic and dynamic music with domain knowledge, and 2) a hierarchical encoding/decoding strategy, which explicitly models the dependency between melodic features. The proposed framework is capable of generating distinct melodies that sounds natural, and the experiments for evaluating generated music clips show that the proposed model outperforms the baselines in human evaluation.1