Recent breakthroughs in heterogeneous integration (HI) using 2.5D and 3D ICs have been key to advances in the semiconductor industry. However, heterogeneous integration has also led to several sources of distrust due to the use of thirdparty IP, testing, and fabrication facilities in the design and manufacturing process. Recent work on 2.5D IC security has focused on attacks that can be mounted through rogue chiplets integrated in the design. Thus, existing solutions implement interchiplet communication protocols that prevent unauthorized data modification and interruption in a 2.5D system. However, none of the existing solutions offer inherent security against IP theft. We develop a comprehensive threat model for 2.5D systems indicating that such systems remain vulnerable to IP theft. We present a method that prevents IP theft by obfuscating the connectivity of chiplets on the interposer using reconfigurable interconnection networks. We further achieve dynamic obfuscation of chiplet interconnects while demonstrating resilience against removal, data-snooping, test-based data leakage attacks. We present an approach to implement reconfigurable chiplet interconnection networks through both centralized and distributed scrambler designs, evaluating the security and implementation benefits of both the architectures. We present a comprehensive methodology to design, implement, and integrate interconnect scramblers in a large 2.5D HI system. We also evaluate the power, performance, and area overhead for both distributed and centralized scramblers.

Back-end-of-line (BEOL) integrated voltage regulators (IVRs) significantly enhance power integrity by reducing on-chip and off-chip dynamic IR-drop compared to traditional off-chip IVR solutions. As semiconductor technologies scale down, power delivery networks increasingly suffer from parasitic limitations, impacting efficiency and performance. While backside power delivery networks (BS-PDNs) offer improvements by mitigating frontside parasitics and power density challenges, conventional architectures remain limited by package-level parasitics in 2.5D interposer systems. To address these constraints, we introduce optimized BEOL IVR structures suitable for BEOL integration, utilizing amorphous tungsten-doped indium oxide (IWO) transistors to enable monolithic 3D integration without additional footprint overhead. Our results demonstrate that BEOL IVRs achieve up to 61% and 54% reductions in on-chip dynamic IR-drop for frontside and backside configurations, respectively, with backside BEOL IVRs providing an additional 18% improvement. Furthermore, BEOL IVRs substantially decrease off-chip dynamic IR-drop by up to 71%, presenting a scalable and technology-node-independent solution for advanced IC designs.

Glass interposers have become a compelling option for 2.5-D heterogeneous integration compared to silicon. It allows 3-D stacking configuration between the embedded dies and the conventional flip-chip dies mounted directly on top at low cost. Furthermore, the interconnect pitch and through-glass-via (TGV) diameter in glass are becoming comparable to their counterparts in silicon. In this study, we investigate the power, performance, area (PPA), signal integrity (SI) and power integrity (PI) advantages of 3-D stacking afforded by glass interposers over silicon interposers. Our research employs a chiplet/package co-design approach, progressing from an register-transfer-level description of RISC-V chiplets to final graphic data system (GDS) layouts, utilizing TSMC 28 nm for chiplets and Georgia Tech’s 3-D glass packaging for the interposer. Compared to silicon, glass interposers offer a$2.6\times $reduction in area, a$21\times $reduction in wire length, a 17.72% reduction in full-chip power consumption, a 64.7% increase in SI and a$10\times $improvement in PI, with a 35% increase in thermal. Furthermore, we provide a detailed comparative analysis with 3-D Silicon technologies. It not only highlights the competitive advantages of glass interposers, but also provides critical insights into each design’s potential limitations and optimization opportunities.

On-chip power planning is a crucial step in chip design. As process nodes advance and the need to supply lower operating voltages without loss becomes vital, the optimal design of the Power Delivery Network (PDN) has become pivotal in VLSI to mitigate IR-drop effectively. To address IR-drop issues in the latest nodes, a back-side power delivery network (BSPDN) has been proposed as an alternative to the conventional front-side PDN. However, BSPDN encounters design issues related to the pitch and resistance of through-silicon vias (TSV s). In addition, BSPDN faces optimization challenges due to the trade-off between rail and grid IR-drop, particularly in the effectiveness of uniform grid design patterns. In this study, we introduce a design framework that utilizes reinforcement learning to identify optimized grid width patterns for individual VLSI designs on the silicon back-side, aiming to reduce IR-drop. We have applied our design approach to various benchmarks and validated its improvement. Our results demonstrate a significant improvement in total IR-drop, with a maximum improvement of up to −19.0% in static analysis and up to −18.8% in dynamic analysis, compared to the conventional uniform BSPDN.

2.5D integration is gaining popularity primarily due to its ability to facilitate intellectual property (IP) reuse. Unlike conventional 2D and 3D approaches, 2.5D integration requires a more complex design and analysis process and is highly sensitive to changes in design parameters. However, research on the sensitivity of 2.5D design parameters is notably scarce, with most studies still concentrating on 2D and 3D. In this paper, we propose an AI-driven model for predicting sensitivity and an optimization methodology for 2.5D parameters, with a particular focus on bump pitch. Our approach employs advanced machine learning models to accurately predict how variations in bump pitch impact the power, performance, and area of chiplets, as well as the footprint, signal integrity, power integrity, and thermal integrity of the interposer layout. We also utilize Bayesian optimization to identify the optimal bump pitch for specific design objectives. Experimental validation of our model demonstrates high accuracy, with average relative errors of 2.69% for interpolation and 2.7% for extrapolation. Furthermore, optimization results, tailored by adjusting weights for various potential design goals, show an average improvement of 11% in area, wire length, and signal integrity-driven optimization, and 9% in power and thermal integrity-driven optimization.

Nanosheet FETs (NSFETs) are attracting attention as promising devices that can replace FinFETs beyond the 5-nm node. Despite the importance of the devices, few studies analyze the impact of NSFETs at the block-level. In this article, we introduce NS3K, the first 3-nm NSFET standard cell library, and examine the results on a block-level scale. In addition to the overall process of designing a full library, we extended the scope of the buried power rail (BPR) to better layout designs. We showed that BPR, originally proposed to overcome power delivery problems, is also an effective solution for standard cell hegith reductions. Using BPR, we highlight that 4-track height standard cell designs have a negligible impact on power delivery and signal routing. Overall chip results show that the 3-nm NSFET outperforms the 5-nm FinFET by −27.4% in power, −25.8% in total wirelength, −8.5% in the number of cells, −47.6% in area, and 34.7% performance, respectively, owing to better device performance and interconnect scaling. However, careful device/layout designs and new interconnect structures must be applied to continue the scaling trend and maximize the advantages of 3-nm technology.

Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology.