Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Junseung Lee

dblp:230/8585 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
1since 2021 · last 2024
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 56% Cloud and datacenter computing · 28% Energy-efficient computing · 17%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cloud and datacenter computing › resource management
datacenter memory management
0.812024
Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers · HPCA 2024
Memory systems
DRAM
0.812024
Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers · HPCA 2024
Memory systems › DRAM
DRAM architecture
0.812024
Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers · HPCA 2024
Energy-efficient computing › power management › memory power management
DRAM power reduction
0.212024
Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers · HPCA 2024
Energy-efficient computing
power management
0.212024
Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers · HPCA 2024

Methods — techniques the papers use, named apart from their topics

runtime mode transition · 0.8
YearPublicationVenuePosition
2024 Agile-DRAM: Agile Trade-Offs in Memory Capacity, Latency, and Energy for Data Centers
abstract
Data centers frequently face significant memory under-utilization due to factors such as infrastructure overprovisioning, inefficient workload scheduling, and limited server configurations. This paper introduces Agile-DRAM, a novel DRAM architecture that addresses this issue by flexibly converting the under-utilized memory capacity into enhanced latency performance and reduced power consumption. Through minor modifications to the conventional DRAM architecture, Agile-DRAM supports multiple operational modes: low-latency, lowpower, and the default max-capacity mode. Notably, Agile-DRAM facilitates agile transitions between these modes in response to workload fluctuations in data centers at runtime. Evaluation results demonstrate that the low-latency mode can boost singlecore execution speed by up to 25.8% and diminish energy usage by up to 22.4%. Similarly, the low-power mode can reduce DRAM standby and self-refresh power by 31.6% and 85.7%, respectively.
Jaeyoon Lee, Wonyeong Jung, Dongwhee Kim, Daero Kim, Junseung Lee, Jungrae Kim
HPCA5