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Dev Narayan Yadav
dblp:231/1149
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5ranked-venue papers
4as first author
4since 2021 · last 2024
0000-0003-2806-3604ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 4 first-author · 4 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Improving Self-Fault-Tolerance Capability of Memristor Crossbar Using a Weight-Sharing ApproachabstractThe ability of resistive memory (ReRAM) to naturally conduct vector-matrix multiplication (VMM), the primary operation carried out in neural networks, has caught the interest of researchers. The memristor crossbar is a suitable architecture to perform VMM and additionally offers benefits like in-memory computation (IMC), low power, and high density. Memristor-based neural networks are typically trained using a mechanism where weight computations are carried out on a host machine and downloaded into the crossbar. However, due to faulty memristors in the crossbar, a cell may not be able to store the exact weight values, which may lead to inference errors. In this paper, we propose a weight-sharing method to improve the self-fault-tolerance capability of memristor crossbar. In order to reduce the impact of faulty memristors, the weights are shared among different layers of memristors in a 3D crossbar. Simulation analyses show considerable improvements in the fault-tolerance capability of the crossbar. Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, F. Lalchhandama, Kamalika Datta, Rolf Drechsler, Indranil Sengupta 0001 |
ATS | 1 |
| 2022 | Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant ApplicationsabstractMemristor-based crossbar architectures have been explored by researchers for neuromorphic computing, where analog vector-matrix multiplication can be carried out in a single time step. In this paper we explore such architectures for carrying out various arithmetic operations. Since the computations are carried out in analog domain, they are affected by fabrication and performance variability of the manufactured devices. As a result, there can be inherent errors during the computation. However, the architecture can be suitable for approximate computing applications where some errors can be tolerated. We have proposed a method for carrying out arithmetic operations with any multiple of k-bit resolution on the crossbar, for some limited values of k. The fault tolerant capability of the proposed architecture is evaluated through experimentation on benchmark datasets. We also perform case studies to analyze the performance of the approach with particular emphasis on approximate computing. The results of the case studies show that certain applications indeed exhibit fault tolerance in presence of faulty memristors. Kamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta 0001, Rolf Drechsler |
VLSI-SoC | 4 |
| 2022 | FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications
Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty 0001, Rolf Drechsler, Indranil Sengupta 0001 |
J. Electron. Test. | 1 |
| 2022 | Feed-Forward learning algorithm for resistive memories
Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty 0001, Rolf Drechsler, Indranil Sengupta 0001 |
J. Syst. Archit. | 1 |
| 2019 | Look-ahead mapping of Boolean functions in memristive crossbar array
Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta |
Integr. | 1 |