This study tackles the challenges of Deepfake detection posed by modern generative models and introduces an integrated architecture that combines Convolutional Neural Network (CNN) with Transformer, enhanced by position-aware modules to improve detection accuracy. While Transformer inherently incorporates positional encoding, CNN lacks explicit spatial modeling capabilities. To address this, our position-aware mechanism fuses RGB images and CNN-derived feature maps with positional encoding information using position-aware attention modules. This integration strengthens the backbone network’s ability to capture and interpret spatial cues. To train and evaluate our model, we constructed a comprehensive dataset of 80,000 facial images—comprising 40,000 AI-generated images from four cutting-edge generative models (StyleGAN3, EG3D, Stable Diffusion XL, and DALL-E 3 XL v2) and 40,000 real images sourced from CelebA-HQ and FFHQ. Experimental results show that our model consistently outperforms baseline approaches on images generated by StyleGAN3, EG3D, Stable Diffusion XL, and DALL-E 3 XL, achieving accuracy gains of 8.49%, 2.93%, 2.40%, and 4.40%, respectively. These findings highlight the model’s superior performance, strong generalization capability, and robustness in detecting Deepfakes generated by state-of-the-art AI models.

This study introduces an Automatic Personality Recognition (APR) model, named XLNet refined-highway-switch network, comprising XLNet, refined highway units, a switching module, and a fully-connected layer. The pretrained XLNet is employed to extract semantic features from text. The refined highway units with the dense connections are explored. Additionally, our study delves into the optimized computation structures between the refined highway and switching module to unearth personality- related features. Notably, this APR model incorporates punctuation and stop words in text, resulting in a notable accuracy boost of up to 6.79%. Through extensive experiments on the integrated datasets which combine My Personality, Essays, and Friends Persona, the proposed model achieves the best average accuracies of64.79% and 64.43% for Big-5 personality traits on English and Chinese versions, respectively, as compared to conventional models. Furthermore, we implemented the proposed APR model in a retrieval-based chatbot, utilizing Jaccard distance to select the most suitable personality responses for interactions, yielding promising results in subject tests. Consequently, the proposed APR model can be widely used in various personalized applications related to personality traits.

In this work, we propose a lightweight Graph Convolution Network (GCN) based on residual attention model successfully applied to the classification task of hand point landmarks. The main highlights of our study involve redefining the standard reference point from the initial outer-coordinate origin to the central position within the palm and improving the node features within the graph. Additionally, we construct a graph network capable of classifying points on the hand. This is achieved through a 2-layer structure, which incorporates attention modules to optimize graph information processing, along with a skip connection to prevent feature uniformity within nodes after numerous hidden layers. The experimental results on the ALS dataset indicate that the proposed model yields remarkably high accuracy rates on both the training and test sets, reaching 97.75% and 97.41%, respectively, while keeping the computational complexity (parameters are only 25,874) at an extremely low level. Moreover, the proposed model exhibited high accuracy rates on the Sign Language MNIST dataset, achieving 99.41% on both accuracy and F1-score. Thus, it has great potential to be deployed on portable devices.

This work adopts camera, lidar and radar sensors to realize 3D object detection of cars and humans in varied and complicated road scenes. Based on the Radar Voxel Fusion Net (RVF-Net) consisting of voxel feature extraction module, feature aggregation module, and detection head module, we extend layers of the voxel feature extraction module with dimensions at a consistent scaling ratio, and increase a prediction head in the detection head module. According to this modified RVF-Net, the depth of the voxel feature extraction module is searched by the proposed unit-sharing one-shot Neural Architecture Search (NAS) scheme where there are five choices of bypass, and one to four copy units for each layer. Only four copy units with conditional links yield five choices for structure searches. Such an approach can minimize the search cost and parameter amount. By using the forward-looking sensing data of nuScenes, the network from the proposed NAS, and the modified RVF-Net can yield superior Average Precisions (AP), more than 2.3% AP increase, than the conventional ones in detecting cars and pedestrians simultaneously. Therefore, the proposed network can effectively accomplish multi-object recognition tasks for self-driving applications.

In this work, we develop the Iterative Multiple-path One-shot Network Architecture Search (NAS), (IMO-NAS), to effectively look for preferable neural network architectures in terms of accuracy, computational complexity, and parameter quantity. Our IMO-NAS includes three steps of full search, random search, and candidate retraining at an iterative operation manner. At each iteration, multiple scaling ratios are employed to multiply the channel numbers at all layers to get many combinations for channel searching where the conventional one-shot NAS cannot alter channel numbers. Based on the super neural network using the mixed depthwise convolutional kernels, IMO-NAS is employed to seek outstanding architectures using Cifar-10 and Cifar-100 datasets where the depthwise convolution layer has multiple blocks to establish multiple paths for search. Simulation results reveal that the architectures found by IMO-NAS can have advantageous performance on accuracy, computational complexity, and memory size, comparing to the conventional deep neural network architectures. Therefore, the proposed IMO-NAS can successfully discover new architectures or fine adjust the popularly-used architectures at fair search time for various artificial intelligence applications.

Comprehensive activity understanding of multiple subjects in a video requires subject detection, action identification, and behavior interpretation as well as the interactions among subjects and background. This work develops the action recognition of subject(s) based on the correlations and interactions of the whole scene and subject(s) by using the Deep Neural Network (DNN). The proposed DNN consists of 3D Convolutional Neural Network (CNN), Spatial Attention (SA) generation layer, mapping convolutional fused-depth layer, Transformer Encoder (TE), and two fully connected layers with late fusion for final classification. Especially, the attention mechanisms in SA and TE are implemented to find out meaningful action information on spatial and temporal domains for enhancing recognition performance, respectively. The experimental results reveal that the proposed DNN shows the superior accuracies of 97.8%, 98.4% and 85.6% in the datasets of traffic police, UCF101-24 and JHMDB-21, respectively. Therefore, our DNN is an outstanding classifier for various action recognitions involving one or multiple subjects.

With consideration of the aging society, the homecare associated with seniors becomes a critical issue in which there is a need for activity recognition of subjects at home. In this work, we propose the computation-affordable recognition system which includes the pre-trained MobileNetV2, temporal bidirectional Gated Recurrent Unit (GRU), Finite State Machine (FSM), and Incremental Majority Voting (IMV), to identify four activities of standing, walking, sitting, and falling. To compromise the accuracy and complexity, the proposed recognition engine adopts the pre-trained MobileNetV2 on ImageNet accompanied with the temporal bidirectional GRU, named as MoBiG. The schemes of FSM and IMV are used to remove the infeasible activity state transitions and to preserve the reasonable continuous activity states, respectively. The application scenario is to adopt a portable camera locating at the living room to record daily activities which are identified by the proposed recognition system embedded on a smart phone. The experimental results reveal that the proposed recognition system yields an average accuracy of 93.1% where the MoBiG and FSM+IMV contributes 91.7% and 1.4%, respectively. Compared to conventional work, the recognition system proposed herein shows the well compromised performance between accuracy and complexity for homecare applications.

On the aged society coming soon, many studies have explored homecare technologies. In this work, the activities at home are captured by a panoramic camera located at the center of a living room, and then analyzed and classified into standing, walking, sitting, falling, and watching television. First, the background subtraction scheme accompanied with shadow removal, and morphological operators of erosion and dilation is used to find out moving subjects, and TV on/off switching. Second, the parameters associated with the subject height, the distance between the camera and subject, and the distance map between subject contour points and centroid are computed to derive features for recognizing activities of standing, walking, sitting, and falling where the Support Vector Machine (SVM) classifier is employed. Additionally, the moving object similar to a parallelogram shape is identified as a TV set. Third, the majority voting in a picture segment of 10 pictures is adopted to determine the final recognition result. When subject sitting and TV on occur simultaneously, this situation is treated as an activity of watching TV. The experimental results reveal that our activity recognition system can achieve the accuracy rate up to 91.1%. The error rates associated with subject height and distance estimations are around 5.5% and 8.2%, respectively. The accuracies of TV on and off detection are close to 95.9% and 100.0%, respectively. Therefore, the proposed activity recognition system exhibits a superior performance for homecare applications.

Attention plays a critical role in effective learning. By means of attention assessment, it helps learners improve and review their learning processes, and even discover Attention Deficit Hyperactivity Disorder (ADHD). Hence, this work employs modified smart glasses which have an inward facing camera for eye tracking, and an inertial measurement unit for head pose estimation. The proposed attention estimation system consists of eye movement detection, head pose estimation, and machine learning. In eye movement detection, the central point of the iris is found by the locally maximum curve via the Hough transform where the region of interest is derived by the identified left and right eye corners. The head pose estimation is based on the captured inertial data to generate physical features for machine learning. Here, the machine learning adopts Genetic Algorithm (GA)-Support Vector Machine (SVM) where the feature selection of Sequential Floating Forward Selection (SFFS) is employed to determine adequate features, and GA is to optimize the parameters of SVM. Our experiments reveal that the proposed attention estimation system can achieve the accuracy of 93.1% which is fairly good as compared to the conventional systems. Therefore, the proposed system embedded in smart glasses brings users mobile, convenient, and comfortable to assess their attention on learning or medical symptom checker.

This brief studies the transimpedance of the regulated cascode (RGC) structure and develops a multilevel active feedback (MLAF) structure to build an inductorless CMOS differential transimpedance amplifier (TIA). The proposed TIA consists of an input stage, a single-to-differential circuit, a gain stage, and an output buffer. The input stage adopts the RGC structure of which transimpedance is theoretically characterized and numerically analyzed to determine design parameters. In the gain stage, the MLAF structure in a hierarchical feedback topology is investigated to increase the bandwidth without inductor peaking. The proposed differential TIA was simulated at the 180-nm, 90-nm, and 28-nm CMOS technologies to verify our design methodology. In addition, the TSMC 180-nm CMOS technology was employed to implement the proposed TIA with a core size of 0.05 mm2, a bandwidth of 7.2 GHz, and a differential transimpedance gain of 1.8 kΩ. Comparing with conventional TIAs, the proposed TIA exhibits the least hardware cost and fairly good performance for applications of 10-Gbit/s optical communications.

To achieve a large bandwidth without inductor peaking, this work presents an inductor-less bandwidth-extension technique to establish Multi-Level Active Feedback (MLAF) structure that is used in a CMOS differential Trans-Impedance Amplifier (TIA). The proposed TIA consists of a trans-impedance stage, a low-pass filter, a gain stage, and an output buffer. The trans-impedance stage adopts the regulated cascode structure. In the gain stage, the MLAF structure which has four cascaded amplifiers and three active feedbacks in a hierarchical feedback topology is employed to effectively increase the bandwidth under a Butterworth response without inductor. The TSMC 0.18µm CMOS technology was used to implement the proposed differential TIA with a core size of 0.05mm2. Without the use of inductor peaking to enlarge the bandwidth, the proposed TIA was measured to have a bandwidth of 7.2GHz, a differential trans-impedance gain of 1.8kΩ and a minimum input sensitivity of 25µA at a bit error rate of 10−12under 231−1 PRBS. Comparing with conventional TIAs, the proposed TIA apparently exhibits a low hardware cost and fairly good performance for applications of 10Gbps optical communications.

This work is to establish an auto-calibration around-view monitoring system to avoid the inconsistent performance from deviations of camera installation. First, a vehicle is parked at a specific area which has a special pattern on the ground. Second, the captured images from four embedded cameras are compared with the reference pattern images to obtain the deviations in angle, X-axis and Y-axis. Finally, these deviations are used to compensate the coefficients of transformation matrices associated with view-point conversion and image stitching. Particularly, the adaptive edge recovery scheme is developed to help on precise alignments. The experimental results show that the proposed system implemented at the TI DaVinci DSP platform can accomplish auto-calibration of a vehicle within 60 seconds and have deviation rates smaller than 38% at stitched regions and 25% at the other regions. Additionally, ±2° deviation errors at angles, X-axis and Y-axis are allowed. Particularly, the proposed system can generate precise 2-meter around-view pictures at a vehicle speed of 30km/h. Therefore, the auto-calibration system proposed herein can be widely applied to vehicle manufacture, verification and repair.

The greatest challenge on monitoring characters from a monocular video scene is to track targets under occlusion conditions. In this work, we present a scheme to automatically track and count people in a surveillance system. First, a dynamic background subtraction module is employed to model light variation and then to determine pedestrian objects from a static scene. To identify foreground objects as characters, positions and sizes of foreground regions are treated as decision features. Moreover, the performance to track individuals is improved by using the modified overlap tracker, which investigates the centroid distance between neighboring objects to help on target tracking in occlusion states of merging and splitting. On the experiments of tracking and counting people in three video sequences, the results exhibit that the proposed scheme can improve the averaged detection ratio about 10% as compared to the conventional work.

This work presents an efficient low-complexity method to compute a 2-D inverse transform flexibly adapted to its end-of-block (EOB) point and corner coefficients. First, the EOB point is obtained from a bitstream or derived from the other parameters. Second, the values of bottom-left and/or top-right corner coefficients before an EOB point are verified as zero or not. Third, the operational mode, based on the EOB point and corner coefficient value(s), determines the reduced dimensional sizes of 1-D inverse transforms in the row and column. Additionally, the computational order of row-after-column or column-after-row is decided to minimize computational complexity. Finally, a 2-D inverse transform at the determined operational mode is computed using simplified 1-D inverse transforms in a row-by-row and column-by-column manner. Particularly, how to implement cycle-efficient structures of inverse transforms in an embedded programmable platform is investigated. Simulation results demonstrate that the proposed method has less computational complexity than conventional methods when executing 2-D inverse transforms at MPEG-2 and H.264/AVC video streams. Notably, the proposed method can reduce computational time required by conventional methods by 14.6%-92.9% at a fairly increased code size. Therefore, the proposed method is very suitable for various applications demanding low-complexity computations of inverse transforms.

In H.264/AVC, multiple reference frames are adopted to enhance inter-predictive coding efficiency of motion estimation/compensation. However, memory cost is also increased with the number of used reference frames. This work presents a size-controllable memory reduction method to accommodate multiple reference frames at a limited memory size. This scheme is to store some of Macro-Blocks (MBs) as compressed data from their partially decoded bit streams, and the other as the reconstructed data. An effective compromise mechanism between amounts of compressed and reconstructed data is developed to meet the memory constraint by minimizing the computation required. Simulation results demonstrate that the proposed method can make a good use of constrained memory to store multiple reference frames of H.264/AVC at I, P and B. As compared to the conventional methods, the proposed method can easily adapt to the amount of the constrained memory, above 95% usage rate, and yield around 3~6 dB improvement on PSNR at fair computation cost.

This work develops an efficiently low-complexity method to compute a 2-dimensional inverse integer transform in H.264/AVC. First, the end-of-block points in 4 × 4 and 8 × 8 blocks are computed and then used to select one of 7 and 15 operation modes for each block, respectively. Second, the computation order of row-after-column and column-after-row used for 1-dimensional inverse integer transforms is adequately chosen to reduce computational complexity. Finally, simplified 1-dimensional inverse integer transforms are employed to accomplish a 2-dimensional inverse integer transform. The simulation results demonstrate that the proposed method can effectively minimize computational complexity of 2-dimensional inverse integer transforms in video streams of H.264/AVC. Particularly, as the smaller is the end-of-block point, the lower is the computational complexity. Therefore, the proposed method can be widely used at various H.264/AVC decoders to reach low-complexity computation.

This work presents a low-power multiplier using a dynamic-range determination (DRD) unit and a modified upper/lower left-to-right (ULLR) structure in the partial-product summation (PPS) unit. Prior to executing a multiplication, effective dynamic ranges of two input data are estimated by the DRD unit to determine that these input data with smaller and larger dynamic ranges are multiplier and multiplicand for Booth decoding, respectively. Such approach can exhibit that partial products in high precision have a high chance of being zero. Due to this phenomenon, the ULLR structure is modified by moving the correction bits from the upper part to the lower part of the PPS unit to reduce switching power. Additionally, various 10-transistor adder cells are investigated to find out the adequate ones in upper and lower parts of the PPS unit for power conservation. By using in-house cells and standard cells of the TSMC 1P6M 0.18-mum CMOS technology, the proposed and conventional multipliers are implemented and simulated by the Power-mill and Time-mill tools. The simulated results demonstrate that the proposed multiplier consumes the least power than the conventional ones in multimedia computing.

The pitch scaling conducts serious attacking on audio watermarked signals because it leads to a desynchronization problem. Based on the proposed analysis- by-synthesis echo watermarking scheme, this work develops a watermark extracting process to improve the robustness performance against pitch-scaling attacks. The positions of embedded echoes are altered in the cepstrum domain due to the pitch-scaling attacks that change the frequency content of audio signals. Hence, it is unable to determine the echo position a priori. In this work, the cepstrum values in a reasonable range of delay offsets affected by pitch-scaling attacks are addressed from auditory point of view. The moving average function is performed on several segments to eliminate the impact of host signals on cepstrum. In this extended range for searching delay offsets, the peak value of the cepstrum is adopted to determine the embedded watermark datum. Experimental results exhibit that the proposed robust echo watermarking scheme can be superior to the conventional audio watermarking schemes under pitch-scaling attacks and other attacks.

In H.264/AVC, many block types are employed to conduct inter and intra coding for determining the best one to achieve good coding efficiency. Accordingly, watermark data can be effectively embedded in these block types that are classified into three groups representing ‘1,’ ‘0’ and no datum. In inter coding, the block types of 16×16, 8×8 and 4×4 represent the watermark bit ‘1,’ and the block types of 16×8, 8 ×16, 8×4 and 4×8 denote the watermark bit ‘0.’ In intra coding, the block type of 8×8 is the watermark bit ‘1,’ and the block types of 16×16 and 4×4 represent the watermark bit ‘0.’ Other block types in inter and intra coding are treated as no datum. In the abovementioned grouping, the hierarchical and interleaving correlations of block types in the same and different groups, respectively, are adopted to minimize the performance distortion. Particularly, each frame is also pre-defined by a watermarking area to preserve coding performance and increase watermarking robustness. The computer simulations demonstrate that the proposed watermarking scheme can effectively hide data at a little increasing bit rate and almost no quality degradation.

Audio watermarking using echo hiding has fairly good perceptual quality. However, security and the tradeoff between robustness and imperceptibility are still relevant issues. This paper presents the echo hiding scheme in which the analysis-by-synthesis approach, interlaced kernels, and frequency hopping are adopted to achieve high robustness, security, and perceptual quality. The amplitudes of the embedded echoes are adequately adapted during the embedding process by considering not only the characteristics of the host signals, but also cases in which the watermarked audio signals have suffered various attacks. Additionally, the interlaced kernels are introduced such that the echo positions of the interlaced kernels for embedding "zero" and "one" are interchanged alternately to minimize the influence of host signals and various attacks on the watermarked data. Frequency hopping is employed to increase the robustness and security of the proposed echo hiding scheme in which each audio segment for watermarking is established by combining the fractions selected from all frequency bands based on a pseudonoise sequence as a secret key. Experimental results indicate that the proposed analysis-by-synthesis echo hiding scheme is superior to the conventional schemes in terms of robustness, security, and perceptual quality.

This work develops an analysis-by-synthesis echo watermarking scheme using frequency hopping to improve robustness and security. First, the host audio signals are transformed and partitioned into several different frequency bands. Each frequency band is then transformed back to the time-domain components that are separated into multiple fractions. Each audio segment is constructed by combining the fractions selected from all frequency bands based on a secret key from a pseudo-noise sequence. The watermarks are embedded in audio segments. In the meantime, the analysis-by-synthesis approach is adopted to perform attacks on the watermarked signals during the watermark embedding process to suggest the adequate amplitudes of echoes. Owing to fractions being scrambled, the chance of watermarks detected and tampered by the third party can be reduced. Additionally, the problem, that it is difficult to correctly embed echoes in long silent intervals, can be overcome by using frequency hopping. Experimental results reveal that the proposed analysis-by-synthesis echo watermarking scheme using frequency hopping can yield better robustness and security than the conventional echo watermarking schemes.

In this work, we propose a low-complexity encryption used in a passive radio frequency identification (RFID) transponder. The proposed encryption functions by using redundant bits and adaptive frequency rates in the transponder to dynamically change the number of the transmitted bits and operation frequencies. The pseudorandom bit sequence is generated by the linear feedback shift register to represent the redundant bits. Additionally, the ring oscillator with a divider and a multiplexer produces a programmable operation frequency. Such approach not only protects the transmitted data under fairly low power consumption, but it also can integrate with the other encryption methods, such as the advanced encryption standard (AES) and the data encryption standard (DES), to further enhance security. Therefore, the encryption scheme proposed herein can be applied in various communication devices to achieve high-security and low-complexity performance

As speech compression technologies have advanced, digital recording devices have become increasingly popular. However, data formats used in popular speech codecs are known a priori, such that compressed data can be modified easily via insertion, deletion, and replacement. This work proposes a content-dependent watermarking scheme suitable for codebook-excited linear prediction (CELP)-based speech codec that ensures the integrity of compressed speech data. Speech data are initially partitioned into many groups, each of which includes multiple speech frames. The watermark embedded in each frame is then generated according to the line spectrum frequency (LSF) feature in the current frame, the pitch extracted from the succeeding frame, the watermark embedded in the preceding frame, and the group index which is determined by the location of the current frame. Finally, some of the least significant bits (LSBs) of the indices indicating the excitation pulse positions or excitation vectors are substituted for the watermark. Conventional watermarking schemes can only detect whether compressed speech data are intact. They cannot determine where compressed speech data are altered by insertion, deletion, or replacement, whereas the proposed scheme can. Experiments established that the proposed scheme used in the G.723.1 6.3 kb/s speech codecs embeds 12 bits in each compressed speech frame with 189 bits, and only decreases the perceptual evaluation of speech quality (PESQ) by 0.11. Additionally, its accuracy in detecting the locations of attacked frames is very high, with only two normal frames mistaken as attacked frames. Therefore, the proposed watermarking scheme effectively ensures the integrity of compressed speech data.

A novel mechanism that flexibly adapts data flows and configures computational units is proposed to establish an application-specific data path in the digital signal processor (DSP) that can efficiently perform multistandard video codecs. Based on this mechanism, the proposed application-specific data path, using the very long instruction word (VLIW) architecture with eight computational units of five arithmetic logic units (ALUs), one multiplier and two load/store units, is designed to perform five adaptive operations according to the characteristics of the low-level functions of MPEG-2, MPEG-4 and H.264/AVC video codecs. Using these adaptive operations, the proposed application-specific data path reduces the number of clock cycles required by the TI TMS320C64x data path to perform the low-level functions of the MPEG-2 video encoder and the H.264/AVC video decoder by 23.10% and 28.43%, respectively, for 30 352times288-pixel Foreman frames. Additionally, considering the operating frequency, the proposed application-specific data path reduces the computation time required by the TI TMS320C64x data path to realize the abovementioned encoder and decoder by 19.86% and 25.41%, respectively. Based on the TSMC 0.18-mum CMOS cell library, the proposed application-specific data path is implemented, and exhibits the highest ratio of computational power to hardware cost among all of the data paths associated with the conventional DSPs in implementing the low-level functions of video codecs

This work presents an automatically-determined region of interest (ROI) scheme embedded in JPEG 2000. The proposed scheme analyzes the image content and then determines the probable ROI masks by examining the significant states of high-frequency subbands generated from embedded block coding with optimized truncation (EBCOT). Additionally, probable ROI masks are constructed in all bit planes of subbands by categorizing sub-blocks as either interesting or uninteresting, smoothing subblocks of interest, and grouping these subblocks based on an or no initial point. The rate-distortion (RD) pairs corresponding to all probable ROI masks are then estimated from the RD distribution during the Tier-2 coding process of EBCOT. Based on these estimations, the Lagrangian multiplier method is employed in the RD function to obtain the optimized ROI mask from the probable masks by minimizing the distortion of the ROI-encoded image at a given bit-rate constraint. ROI-encoded images obtained using the proposed scheme outperform ROI-encoded images obtained via the conventional schemes using fixed-square and object-segmentation masks, as judged by subjective visual perception and objective measurement in terms of peak signal-to-noise ratio. Particularly, the proposed scheme can easily adapt the ROI region with varied sizes and shapes according to the bit-rate constraint whereas the conventional schemes only adopt the fixed-square region and fixed segmented objects. Furthermore, when the proposed scheme is applied to motion JPEG 2000 for video compression, the centroid of the ROI mask in the previous frame can be used as an initial point for merging the subblocks of interest in the current frame to track the ROI masks in a video sequence. Therefore, the proposed scheme can easily be employed to improve the perceptual and objective performance in the ROI coding associated with JPEG 2000 and motion JPEG 2000.

Watermarking using the echo hiding technique can have fairly good performance in perceptual quality. However, the tradeoff between robustness and imperceptibility still is a challenge work. In this study, the analysis-by-synthesis echo hiding scheme based on the mirrored kernels is proposed to determine the appropriate amplitudes of the embedded echoes with considering the characteristics of host signals. The analysis-by-synthesis technique is to perform attacks on the watermarked signals during the watermark embedding process to suggest the amplitude parameters. Additionally, the attacks are modeled by the Gaussian white noise. To avoid the embedded watermarks depending on the host signals and reduce the impact of various attacks, the positions of mirrored kernels for embedding "0" and "1" are inter-changed alternatively. The experimental results demonstrate that the proposed analysis-by- synthesis echo hiding scheme is superior to the conventional schemes in terms of robustness and perceptual quality.

In this work, a 10Gb/s CMOS transimpedance amplifier using the source-follower regulated cascode and double active feedback schemes is developed based on the TSMC 0.18/spl mu/m CMOS technology. The proposed transimpedance amplifier includes a transimpedance stage, gain stage, and open-drain output buffer. By using the source-follower regulated cascode structure, the proposed transimpedance stage not only compensates input capacitances of the photodiode and input bonding pad but also avoids from the headroom effect. Additionally, the gain stage employs the double three-order active feedback to provide a high-speed and large driving-capability buffer between the transimpedance stage and the open-drain output buffer. At a supply voltage of 1.8V, the proposed transimpedance amplifier has a bandwidth about 7. 7 GHz with a total transimpedance gain of 1.12k/spl Omega/, the group delay about /spl plusmn/ 25ps, the average input-referred noise current of 20/spl mu/A//spl radic/Hz, and the maximum allowed input capacitance of 300fF. The core size of the proposed transimpedance amplifier is 300/spl mu/m /spl times/ 100/spl mu/m. As compared to the conventional ones, the proposed transimpeadance amplifier can have a larger input capacitance and lower hardware cost at a similar receiving performance for 10GB/s optical data communication.

A probability associated with the population fitness is used in a genetic algorithm (GA) to terminate the evolution. The theoretically probabilistic derivation of population fitness reveals that the probability is inversely proportional to the individual variation and directly proportional to the evolving error between the average individual and the global optimum of the objective function. Based on the probability, GA switches its operation mode between the genetic operation and the population regeneration. A modified genetic algorithm with a termination strategy is proposed to find the global optima of five objective functions and thus validate the proposed probability of population fitness.

A particle swarm optimization (PSO) incorporating a preferential velocity-updating mechanism is proposed in this paper to improve the evolutionary performance. Based on the evolution experience from all particles in the swarm, the evolution of the proposed PSO is directed by imposing preference on different parts of the velocity-updating rule to all particles. The particles lying far away from the global best position are provided with more spontaneity to search, while ones close to the global best position are provided with better exploitation capability to search toward the direction of the global best position. Simulation results via the proposed approach to optimize 14 objective functions, estimating the reduced-order IIR have shown that satisfactory performance can be obtained over conventional PSO variants.

In conventional echo watermarking methods, the robustness of watermarks could be improved by increasing the amplitudes of the echo signals, also known as the decay rates, but at the expense of sacrificing audio quality. The objective of this work is to achieve a better audio quality and preserve the robustness of the watermarks. Along with the proposed analysis-by-synthesis approach, there are two other considerations used to adjust the appropriate decay rates of each audio signal segment. One is the characteristics of the audio signals after watermarking, and the other being the accuracy of the watermarks that are decoded and recovered after MP3 attacks on the watermarked audio signals. Looking at the average decay rates and the signal-to-noise ratios, the proposed method exhibits better audio quality than those of the conventional method. Furthermore, the experimental results show that the recovery accuracy rates of watermarks from the watermarked audio signals after attacks are much higher than those of the conventional method.

The paper proposes a robust fully-automatic segmentation scheme based on a modified edge-following technique. First, an image frame is partitioned into many B/spl times/B-pixel blocks. In each block, the pixel point having the maximum gray-level difference from its neighboring point can be selected as the initial point. Additionally, the threshold can be determined automatically according to the histogram of gray-level difference values of initial points with their neighboring points. By using this threshold value, the edge points are determined from the initial points. Based on edge points, the modified edge-following technique with multiple direction detections is performed to find the closed-loop contours. The whole process is fully automatic, so that the disadvantages of both snake and live wire on the fly (LWOF) schemes on manually selecting the initial contours and points, and of the watershed on manually setting the threshold value can be dramatically improved at the same time. Owing to the rapid and fully-automatic segmented results, the proposed scheme is more robust and applicable on various image and video applications than conventional segmentation schemes.

In this work, a low-power multiplication accumulation calculation (MAC) unit is proposed. In the multiplication process, the scheme of Booth encoding one of two input data with the smaller effective dynamic range is utilized to increase the probability of partial products being zero. In the addition process, the scheme is to make an adder operating at the larger effective dynamic range of two input data. The switching activities of this adder in the non-effective range can be minimized. These two schemes are integrated to design the proposed low-power MAC unit. By using the cell-based library of the TSMC 0.35 um CMOS technology, the proposed and conventional MAC units based on the Farag, Kwon and modified Yu architectures are implemented. In practical applications, power analysis was conducted on operations of the G.723.1 speech coder, ADPCM audio coder and wavelet transform in JPEG 2000. The proposed MAC unit using the modified Yu architecture can save power dissipation up to 35.3%, 21.6%, and 36.3%, respectively, in these three applications. Taking into consideration of the product factor of power consumption, hardware area and critical delay, the proposed MAC units still have better performance than the conventional ones. Therefore, the proposed MAC unit can consume low power for multimedia computing at a little increase of the hardware area.

This work presents low-power 2's complement multipliers by minimizing the switching activities of partial products using the radix-4 Booth algorithm. Before computation for two input data, the one with a smaller effective dynamic range is processed to generate Booth codes, thereby increasing the probability that the partial products become zero. By employing the dynamic-range determination unit to control input data paths, the multiplier with a column-based adder tree of compressors or counters is designed. To further reduce power consumption, the two multipliers based on row-based and hybrid-based adder trees are realized with operations on effective dynamic ranges of input data. Functional blocks of these two multipliers can preserve their previous input states for noneffective dynamic data ranges and thus, reduce the number of their switching operations. To illustrate the proposed multipliers exhibiting low-power dissipation, the theoretical analyzes of switching activities of partial products are derived. The proposed 16 /spl times/ 16-bit multiplier with the column-based adder tree conserves more than 31.2%, 19.1%, and 33.0% of power consumed by the conventional multiplier, in applications of the ADPCM audio, G.723.1 speech, and wavelet-based image coders, respectively. Furthermore, the proposed multipliers with row-based, hybrid-based adder trees reduce power consumption by over 35.3%, 25.3% and 39.6%, and 33.4%, 24.9% and 36.9%, respectively. When considering product factors of hardware areas, critical delays and power consumption, the proposed multipliers can outperform the conventional multipliers. Consequently, the multipliers proposed herein can be broadly used in various media processing to yield low-power consumption at limited hardware cost or little slowing of speed.

This work proposes a scheme to expedite the process of finding the contour of an object. Regardless of the image size or whether if the target area is closed-end, the user only needs to select two initial points near the boundaries of an object to search for its contour. Time spent in manually selecting the initial points would then be greatly reduced. By using the dynamic direction prediction to further analyze the neighboring points near the boundary points, the proposed scheme effectively reduces the computational complexity. Furthermore, the drawback of being easily interfered with noises, as seen in the conventional segmentation schemes, is also improved in the proposed scheme. Hence, the scheme proposed herein can be widely used for various applications of image segmentation to achieve high-speed and reliable performances.

In this work, the instruction-level and function-level profile analyses of a MPEG-4 video encoder are performed to design a reconfigurable digital signal processor (DSP) architecture. According to the result from the instruction-level profile analysis, the proposed DSP architecture would be lined up with 5 arithmetic logic units (ALUs), 1 multiplier, and 2 load/store units. Such a line-up in the computation units would allow the proposed DSP architecture to have a better parallel processing capability and a higher hardware usage rate in realizing the MPEG-4 video encoder. The result from the function-level profile analysis reveals that the function of motion estimation requires the most computation power. Hence, the proposed DSP architecture reconfigures 4 ALUs and a multiplier to become a functional unit for high parallel processing of motion estimation. This hardware design of motion estimation is primarily dependent on the adders and multiplier of the proposed DSP architecture, plus a few control circuits to convert the computation units. Such arrangement would have less hardware cost than in conventional video processors with specialized functional units for motion estimation. Lastly benchmark analysis and comparison are done between the proposed DSP architecture and TI TMS320C64x architecture. In processing the MPEG-4 video encoder, the proposed DSP architecture is as much as 80% more efficient in computation than the TI TMS320C64x architecture.

To design a power-efficient digital signal processor, this study develops a fundamental arithmetic unit of a low-power adder that operates on effective dynamic data ranges. Before performing an addition operation, the effective dynamic ranges of two input data are determined. Based on a larger effective dynamic range, only selected functional blocks of the adder are activated to generate the desired result while the input bits of the unused functional blocks remain in their previous states. The added result is then recovered to match the required word length. Using this approach to reduce switching operations of noneffective bits allows input data in 2's complement and sign magnitude representations to have similar switching activities. This investigation thus proposes a 2's complement adder with two master-stage and slave-stage flip-flops, a dynamic-range determination unit and a sign-extension unit, owing to the easy implementation of addition and subtraction in such a system. Furthermore, this adder has a minimum number of transistors addressed by carry-in bits and thus is designed to reduce the power consumption of its unused functional blocks. The dynamic range and sign-extension units are explored in detail to minimize their circuit area and power consumption. Experimental results demonstrate that the proposed 32-bit adder can reduce power dissipation of conventional low-power adders for practical multimedia applications. Besides the ripple adder, the proposed approach can be utilized in other adder cells, such as carry lookahead and carry-select adders, to compromise complexity, speed and power consumption for application-specific integrated circuits and digital signal processors.

In this paper, we propose a computation scheme to reduce computational complexities of the discrete cosine transform (DCT) and quantization. Based on the relationship between block contents and the quantization table, the end-of-block (EOB) point is predicted in the 2-dimensional 8x8 DCT computation structure for the H.263 video encoder. Using the predicted EOB point, the DCT calculation structure is minimized and the number of points required for quantization is also decreased. The top-down, binary-tree and bottom-up techniques of searching the EOB point are explored where the adequate searching points are utilized to minimize the truncation error of the DCT computation structure. As compared to the fixed 32-coefficient and 64-coefficient DCT schemes, the proposed scheme takes the least computational complexity. The quality of the decoded video using the proposed scheme is better than that using the 32-coefficient DCT scheme and close to that using the 64-coefficient DCT scheme. Therefore, the computation scheme proposed herein can be widely utilized in video and image compression applications.

In this paper, we propose a low-complexity computation scheme of Discrete Cosine Transform (DCT) and quantization, which is adaptive to block contents of image frames. With consideration of maintaining the quality of the decoded image and reducing the computational complexity, we take a closer look at the relationship between block contents and the quantization table. Based on this relationship to predict the number of DCT coefficients required for calculation, we develop an adaptive scheme to update the DCT calculation structure. Comparing our scheme in deriving DCT coefficients with that of DCT calculation for a fixed number of coefficients. Our scheme can compromise image qualities with computational complexities. In other words, the proposed scheme could adjust the DCT calculation complexity depending on the image contents. The image quality from our scheme is comparable to that of a complete 64-coefficient DCT calculation process. Therefore, our proposed scheme to calculate DCT and quantization, with abilities to reduce the computational complexity and preserve the picture quality, is suitable and applicable in video and image compression used nowadays.

The programmable FIR architectures using different radix numbers of the Booth algorithm are explored. Based on the radix-2' Booth algorithm, the modified transposed direct-form FIR architectures with and without programmable dynamic ranges of input data and filter coefficients are formulated. The complexities, throughput rates and complexities per throughput rate of the FIR architecture with and without various programmable dynamic data ranges are analyzed in different radix numbers of the Booth algorithm. According to our analyses: the radix-4 approach would be a good choice to achieve a low hardware complexity. For a high throughput rate, the radix 16 or higher radix number of the Booth algorithm should be considered. But if complexity per throughput rate is important, then the radix-8 and radix-16 approaches may be preferred in the FIR architecture without and with programmable dynamic data ranges: respectively. Therefore, users can apply our results to determine a suitable radix number of the Booth algorithm for designing the optimized FIR architecture with consideration of the chip area, speed, throughput rate, power consumption and so on.

In this paper, we developed a low-power and high-frequency transceiver by using the TSMC 0.35 um CMOS single-poly-four-metal technology. The proposed transceiver includes a photo-detector and a laser diode driver where the photodiode and laser diode can be packaged by using the flip-chip connections. The proposed photo-detector indirectly senses the photo current and uses a bias voltage to control a current source and to provide an adequate reversed bias voltage of the photodiode. The laser diode driver is implemented by using a current mirror and two gate-control transistors. A prototype chip of two 2/spl times/2 receivers and two 2/spl times/2 transmitters are implemented with a die size of 2.4 mm/spl times/2.4 mm where the CMOS photodiodes with ring-type electrodes are designed. At a supply voltage of 3.3 V, the proposed photo-detector and laser diode driver can be operated at a clock frequency of 1 GHz with power dissipation of 3.8 mW and 5.0 mW, respectively, where the photodiode provides 100 /spl mu/A and the laser diode has a threshold current of 0.6 mA for a light wavelength of 850 nm. Therefore, the proposed transceiver can be widely used in low-power and high-frequency chip-to-chip interconnection systems.

This work presents a low-complexity high-performance motion estimation method using a one-dimensional (1-D) gradient descent search. The proposed method consists of initial-point determination, initial-direction determination, a gradient descent search using variable step sizes and conjugate directions, and convergence checking. For each block, one of the original and predictive points with the best block-matching performance is the initial point where the predictive ones are motion vectors of its neighboring four searched blocks. In addition, the searching path is optimized by determining the initial direction based on the vector from the original point to the initial point. After determining the initial point and direction, the gradient descent search using variable step sizes and conjugate directions is performed until the searched point attains a better performance than its neighboring points. Moreover, variable step sizes for moving and slowly moving, or stationary blocks, are well addressed to improve the convergence performance of a gradient descent search. Simulation results demonstrate that our method yields a superior performance in terms of computational complexity and picture quality as compared to the three-step search, 1-D full search, block-based gradient descent search, and one-at-a-time search methods.

This work developed a modified direct form based on the radix-4 Booth algorithm to realize a finite impulse response (FIR) architecture with programmable dynamic ranges of input data and filter coefficients. This architecture comprises a preprocessing unit, data latches, configurable connection units, double Booth decoders, coefficient registers, a path control unit, and a postprocessing unit. Programmable dynamic ranges of input data and filter coefficients can be any positive even numbers or multiple of a word length of coefficient registers, using configurable connection units or a path control unit, respectively. In particular, the proposed architecture employs only data-path controls to accomplish programmable operations, without changing word lengths and components of data latches and filter taps. A practical 8-bit and 16-bit FIR processor has also been implemented by using the TSMC 5 V 0.6 /spl mu/m CMOS technology. It is suitable for operations of asymmetric, symmetric, and anti-symmetric filters at 64, 63, 32, 31, and 16 taps, and is well explored to optimize its functional units. The proposed processor has throughput rates of 50 M and 25 M samples/s for 8-bit and 16-bit input data of various filter applications, respectively.

Based on the radix-4 Booth algorithm, we developed a highly-scaleable symmetric/asymmetric finite impulse response (FIR) architecture which comprises preprocessing unit, data latches, configurable connection units, double Booth decoders, coefficient registers, a path control unit, and a post-processing unit. In order to achieve scaleability, the configurable connection units between data latches and the double Booth decoders have been effectively addressed. The precision of filter coefficients is adjustable by using a path control unit. The double Booth decoder with single and double Booth decoding is efficiently implemented. Especially, the proposed architecture only employs data-path controls to accomplish the scaleable operations without changing word lengths and components of data latches and filter taps. A practical FIR processor, which can accommodate dynamic ranges of 8 and 16 bits of input data and filter coefficients was implemented by using the COMPASS 5 V cell library in the TSMC 0.6 /spl mu/m CMOS technology. This processor supports ten different operation modes of asymmetric, symmetric, and anti-symmetric filter coefficients at 64, 63, 32, or 16 taps for various industrial applications.

A highly-scaleable FIR architecture based on the radix-4 Booth algorithm has been designed with scaleable dynamic ranges of input data and filter coefficients. The radix-4 Booth algorithm is demonstrated to have a lower hardware complexity and a fairer throughput rate than the other radix approaches. In order to achieve scaleability, the configurable-connection function between latches of input data, and filter taps has been explored. The precision of filter coefficients is adjustable by using a path-control function. Especially, the proposed architecture only employs data-path controls to realize the scaleable issue without changing the word lengths and components of input latches and filter taps. The pre-processing unit for manipulating input data and post-processing unit for computing accumulation results have been realized to support scaleable operations. Based on our architecture in a chip design, the cascaded configuration between chips is also easily accomplished for many industrial applications.

A self-organization neural network architecture is used to implement vector quantization for image compression. A modified self-organization algorithm, which is based on the frequency-sensitive cost function and centroid learning rule, is utilized to construct the codebooks. Performances of this frequency-sensitive self-organization network and a conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results. Good adaptivity for different statistics of source data can also be achieved.>

The VLSI architecture for an adaptive vector quantizer is presented. The adaptive vector quantization method does not require a-priori knowledge of the source statistics and the pre-trained codebook. The codebook is generated on the fly and is constantly updated to capture local textual features of data. The source data are directly compressed without requiring the generation of codebook in a separate pass. The adaptive method is based on backward adaption without any side information. The speed of data compression by using the proposed adaptive method is much faster than that by using the conventional vector quantization methods. The algorithm is shown to reach the rate distortion function for memoryless sources. In image processing, most smooth regions are matched by the code vectors and most edge data are preserved by using the block-data interpolation scheme. The VLSI architecture consists of two move-to-front vector quantizers and an index generator. It explores parallelism in the direction of the codebook size and pipelining in the direction of the vector dimension. According to the circuit simulations using the popular SPICE program, the computation power of the move-to-front vector quantizer can reach 40 billion operations per second at a system clock of 100 MHz by using 0.8 /spl mu/m CMOS technology. It can provide a computing capability of 50 Mpixels per second for high-speed image compression. The proposed algorithm and architecture can lead to the development of a high-speed image compressor with great local adaptivity, minimized complexity, and fairly good compression ratio.>

A high-speed image compression VLSI processor based on the systolic architecture of difference-codebook binary tree-searched vector quantization has been developed to meet the increasing demands on large-volume data communication and storage requirements. Simulation results show that this design is applicable to many types of image data and capable of producing good reconstructed data quality at high compression ratios. Various design aspects of the binary tree-searched vector quantizer including the algorithm, architecture, and detailed functional design are thoroughly investigated for VLSI implementation. An 8-level difference-codebook binary tree-searched vector quantizer can be implemented on a custom VLSI chip that includes a systolic array of eight identical processors and a hierarchical memory of eight subcodebook memory banks. The total transistor count is about 300000 and the die size is about 8.67/spl times/7.72 mm/sup 2/ in a 1.0 /spl mu/m CMOS technology. The throughput rate of this high-speed VLSI compression system is approximately 25 Mpixels per second and its equivalent computation power is 600 million instructions per second.>

An adaptive method for lossy data compression and the associated VLSI architecture have been developed. This scheme does not require a-priori knowledge of the source statistics and codebook training. The codebook is generated on the fly and is constantly updated to capture local textual features of data. The algorithm is proven to reach rate distortion function for memoryless sources. The authors also propose a computing architecture which consists of a vector quantizer and an encoded-data generator. By using this method, a high-speed VLSI processor with good local adaptivity, less complexity and fair compression ratio can be achieved.>

A self-organization neural network architecture is used to implement the vector quantizer for image compression. A modified self-organization algorithm, which is based on the frequency upper-threshold and centroid learning rule, is utilized for constructing the codebooks. The performances of the self-organization network and the conventional algorithm for vector quantization are compared. This algorithm yields near-optimal results and is computationally efficient. The self-organization network approach is suitable for adaptive vector quantizers. The self-organization network approach uses massively parallel computing structures and is very promising for VLSI implementation.>

An adaptive electronic neural network processor has been developed for high-speed image compression based on a frequency-sensitive self-organization algorithm. The performance of this self-organization network and that of a conventional algorithm for vector quantization are compared. The proposed method is quite efficient and can achieve near-optimal results. The neural network processor includes a pipelined codebook generator and a paralleled vector quantizer, which obtains a time complexity O(1) for each quantization vector. A mixed-signal design technique with analog circuitry to perform neural computation and digital circuitry to process multiple-bit address information are used. A prototype chip for a 25-D adaptive vector quantizer of 64 code words was designed, fabricated, and tested. It occupies a silicon area of 4.6 mmx6.8 mm in a 2.0 mum scalable CMOS technology and provides a computing capability as high as 3.2 billion connections/s. The experimental results for the chip and the winner-take-all circuit test structure are presented.

A trainable VLSI neuroprocessor for adaptive vector quantization based upon the frequency-sensitive competitive learning algorithm has been developed for high-speed high-ratio image compression applications. Simulation results show that such an algorithm is capable of producing good-quality reconstructed image at compression ratios of more than 20. This design includes a fully parallel vector quantizer and a pipelined codebook generator which obtains a time complexity O(1) for each quantization vector. A 5*5-dimensional vector quantizer prototype chip has been designed, fabricated and tested. It contains 64 inner-product neural units and an extendable winner-take-all block. This mixed-signal chip occupies a compact Si area of 4.6*6.8 mm/sup 2/ in 2.0- mu m scalable CMOS technology.>