This paper presents an approach to the mitigation of harmonic distortions in wideband current-steering digital-to-analog converters (DACs). This approach enables code-independent constant-switching-activity data-weighted-averaging (CSA-DWA) with the extra area and power overhead by exploiting redundant current sources. With CSA-DWA, a 16-bit 4.0-GS/s calibration-free DAC is designed in 65 nm CMOS. To achieve high-speed low-complexity CSA-DWA decoding, the most-significant-bit (MSB) segment is set to 5 bits. The MSB switching activities are regulated to be constant with 1-bit randomized switching activity to minimize the non-linearity due to the MSB switching activity truncation errors in the CSA-DWA decoder. Furthermore, a power delivery scheme is adopted to reduce the IR-drop mismatch between the switching elements. Experimental results show that this DAC achieves$>$70 dBc spurious-free dynamic range (SFDR) and$< -80$dBc third-order intermodulation distortion (IM3) up to 1 GHz. With the proposed CSA-DWA, SFDR and IM3 are improved by 4–15 dB and 5–14 dB, respectively, across the Nyquist band.

Time interleaving (TI) is an effective approach to higher speed conversion of current-steering digital-to-analog converters (DACs). However, achieving high linearity performance for these TI DACs is challenging during interleaving synchronization, output current summation, and parasitic capacitance control. This article exploits the design of a 6.0-GS/s 14-bit two-channel time-interleaved DAC in a 65-nm CMOS process for communication systems. A novel asymmetric current-tree summation network is proposed to reduce the current summation nonlinearity in the DAC. A differential clock phase and duty-cycle calibration scheme is also adopted while achieving low complexity. Furthermore, a current source layout optimization scheme is proposed that significantly reduces the parasitic capacitance of interleaving switches and improves the linearity. Measurement results of the fabricated DAC show 6–20-dB spurious-free dynamic range (SFDR) improvement with the proposed techniques, achieving >60-dB SFDR up to 1355 MHz and >50-dB SFDR up to the Nyquist.

This paper presents dynamic switching sequence (DSS) for current-steering digital-to-analog converters (DACs). Unlike conventional static switching sequence (SSS), the proposed DSS dynamically selects from pre-defined switching sequences, and achieves a minimized integral nonlinearity (INL) that is even lower than the lower bound of traditional SSS. Moreover, it works effectively with the digital pre-distortion (DPD) technique to further reduce the residual nonlinearity. Simulation results of a 16-bit segmented DAC show an average INL reduction from 37.9 LSBs (SSS, with 17.7 LSBs as the lower bound) and 10.3 LSBs (SSS+DPD, normalized), to 8.2 LSBs (with DSS) and 0.2 LSBs (DSS+DPD).