Smart contracts are a promising means of formalizing and reliably enforcing agreements between entities using distributed ledger technology (DLT). Research has revealed that a significant number of smart contracts are subject to programming flaws, making them vulnerable to attacks and leading to detrimental effects, such as asset loss. Researchers and developers call for a thorough analysis of challenges to identify their causes and propose solutions. To respond to these calls, we conducted two literature reviews and diverse expert interviews and synthesized scattered knowledge on challenges and solutions. We identified 29 challenges (e.g., code visibility, code updateability, and encapsulation) and 60 solutions (e.g., gas limit specification, off-ledger computations, and shadowing). Moreover, we developed 20 software design patterns (SDPs) in collaboration with smart contract developers. The SDPs help developers adjust their programming habits and thus support them in their daily development practices. Our results provide actionable knowledge for smart contract developers to overcome the identified challenges and offer support for comparing smart contract integration concepts across three fundamentally different DLT protocols (i.e., Ethereum, EOSIO, and Hyperledger Fabric). Moreover, we support developers in becoming aware of peculiarities in smart contract development and the resulting benefits and drawbacks.

In this paper, we present a new, quasi-parallel approach to the loose routing problem for gate array LSI design. It is based on a new modeling for the decomposition problem of each net using a compact net graph which maps sets of feed-throughs instead of individual ones. The loose routing is done by calculation of a minimum spanning tree in this net graph and by a proper embedding of the tree as a set of single-channel subnets and feed-throughs. Moreover, a hierarchical approach is proposed, leading to a quasi-parallel embedding of all nets. It also allows different routing priorities for single connections within multiterminal nets. The hierarchical loose routing concept presented here is implemented in the fully integrated gate array design system MEGA and has been successfully tested on several industrial design examples.