In recent years, electronic design automation methodologies based on hierarchical multilevel bottom-up (BU) design approaches are emerging and successfully applied for RF system design. In this article, we propose a design automation methodology for the synthesis of millimeter-wave (mm-wave) systems via BU approaches, including sizing and layout generation. First, uniformly sampled passive and active component libraries with prepared layouts and S-parameter files are constructed during the offline preparation stage. Second, the BU sizing from the device level to the system level has been demonstrated via multiobjective optimization algorithms, while an improved Euclidean mapping strategy is proposed to efficiently search over circuit-level Pareto-optimal fronts (POFs) in the system-level optimization. Third, the parameterized DRC/LVS clean layout can be hierarchically generated for the system-level POFs. Compared to flat optimization at the system level, the proposed method greatly reduces the size of the search space with the highest accuracy possible and can be used for the synthesis of complex mm-wave systems. The proposed method achieves a$10\times $runtime speedup in the system-level optimization with better optimization results.

Central neuropathic pain (CNP) after spinal cord injury (SCI) is related to the plasticity of cerebral cortex. The plasticity of cortex recorded by electroencephalogram (EEG) signal can be used as a biomarker of CNP. To analyze changes in the brain network mechanism under the combined effect of injury and pain or under the effect of pain, this paper mainly studies the changes of brain network functional connectivity in patients with neuropathic pain and without neuropathic pain after SCI. This paper has recorded the EEG with the CNP group after SCI, without the CNP group after SCI, and a healthy control group. Phase-locking value has been used to construct brain network topological connectivity maps. By comparing the brain networks of the two groups of SCI with the healthy group, it has been found that in the [Formula: see text] and [Formula: see text] frequency bands, the injury increases the functional connectivity between the frontal lobe and occipital lobes, temporal, and parietal of the patients. Furthermore, the comparison of brain networks between the group with CNP and the group without CNP after SCI has found that pain has a greater effect on the increased connectivity within the patients' frontal lobes. Motor imagery (MI) data of CNP patients have been used to extract one-dimensional local binary pattern (1D-LBP) and common spatial pattern (CSP) features, the left and right hand movements of the patients' MI have been classified. The proposed LBP-CSP feature method has achieved the highest accuracy of 98.6% and the average accuracy of 91.5%. The results of this study have great clinical significance for the neural rehabilitation and brain-computer interface of CNP patients.

In this article, we propose an efficient surrogate-assisted constrained multiobjective evolutionary algorithm for analog circuit sizing via self-adaptive incremental learning. The proposed approach reduces the total optimization time in four aspects. First, by reusing the previously trained models, the incremental learning technique is introduced to reduce the time complexity of training the Kriging model from$O(n^{3})$to$O(n^{2})$, where$n$is the number of training points. Second, a self-adaptive strategy to control when to update hyperparameters is proposed to further reduce the training time of the Kriging model. Third, our method is driven by prescreening the most promising population instead of internal optimization which saves the prediction time of the Kriging model. Fourth, the maximin distance-based expected improvement matrix criterion is introduced as the acquisition function to formulate multiple objectives into a scalar function, reducing the sorting time to rank population. Experimental results on three real-world circuits demonstrate that compared with the state-of-the-art multiobjective Bayesian optimization, our method achieves a speedup of up to$13\times $in total runtime without surrendering optimization results. To be more specific, our method reduces the training time of the Kriging model by 96%, the prediction time by 99%, and the sorting time to rank population by up to 92%. Compared with NSGA-II, there is up to$6\times $speedup in terms of the total runtime with better results.

In this paper, we propose an efficient Kriging-based constrained multi-objective evolutionary algorithm for analog circuit synthesis via self-adaptive incremental learning. The incremental learning technique is introduced to reduce time complexity of training the Kriging model from$O(n^{3})$, to$O(n^{2})$, where$n$is the number of training points. The proposed approach reduces the total optimization time in three aspects. First, by reusing the previously trained models, a self-adaptive incremental learning strategy is applied to reduce the training time of the Kriging model. Second, we use non-dominated sorting and modified crowding distance to prescreen the most promising one to be simulated, which largely reduce the number of simulations. Third, as there is no internal optimization, the prediction time of the Kriging model is saved. Experimental results on two real-world circuits demonstrate that compared with the state-of-the-art multi-objective Bayesian optimization, our method can reduce the training time of Kriging model by 95% and the prediction time by 99.7% without surrendering optimization results. Compared with NSGA-II and MOEA/D, the proposed method can achieve up to 10X speed up in terms of the total optimization time while achieving better results.

The impact of process variation to advanced integrated circuits has become increasingly significant. Traditional sampling based yield analysis and optimization always require large amount of expensive simulations. This paper proposes an All Sensitivity Adversarial Importance Sampling (ASAIS) yield optimization method, which avoids samplings in outer optimization based on sensitivity. Moreover, Fast Sensitivity Importance Sampling (FSIS) yield analysis method is adopted as inner yield analysis to eliminate the sampling using transient sensitivity analysis. Experiments on SRAM show ASAIS generates more than 90X speedup of the entire yield optimization process, while FSIS speedup 3X-I5X over existing methods.