Storytelling infographics are a powerful medium for communicating data-driven stories through visual presentation. However, existing authoring tools lack support for maintaining story consistency and aligning with users’ story goals throughout the design process. To address this gap, we conducted formative interviews and a quantitative analysis to identify design needs and common story-informed layout patterns in infographics. Based on these insights, we propose a narrative-centric workflow for infographic creation consisting of three phases: story construction, visual encoding, and spatial composition. Building on this workflow, we developed InfoAlign, a human–AI co-creation system that transforms long or unstructured text into stories, recommends semantically aligned visual designs, and generates layout blueprints. Users can intervene and refine the design at any stage, ensuring their intent is preserved and the infographic creation process remains transparent. Evaluations show that InfoAlign preserves story coherence across authoring stages and effectively supports human–AI co-creation for storytelling infographic design.

ABSTRACT Hard disk drive (HDD) failures in large‐scale distributed storage systems can lead to severe data loss and service disruptions. While failure prediction using SMART data is a critical mitigation strategy, existing models often inadequately capture the gradual degradation of disk health, suffering from limitations in feature selection and temporal modeling. To overcome these challenges, this paper proposes GRUHP, a Gated Recurrent Unit‐based Health Prediction model integrated with an adaptive feature selection mechanism. GRUHP efficiently handles high‐dimensional Self‐Monitoring, Analysis, and Reporting Technology (SMART) data by dynamically identifying the most discriminative features, while its GRU architecture fully leverages temporal patterns for accurate health assessment. The model also incorporates dedicated modules for continuous health state evaluation and fault diagnosis. Extensive experiments on two public datasets demonstrate that GRUHP achieves an average precision of 93.4%, recall of 99.3%, and F 0.5 ‐score of 94.5%, with a false positive rate of only 0.7%. These results confirm that the proposed method, through its synergistic feature selection and temporal modeling, offers a robust and highly applicable solution for proactive failure prediction in real‐world storage environments.

This paper presents an ultra-low power 915 MHz Local Oscillator (LO) with adaptive frequency calibration algorithm for IoT Wake-Up Receivers (WURs). The proposed algorithm can adaptively adjust and minimize the calibration time of each bit oscillator tuning word (OTW) as well as the number of OTWs that require re-calibration after open-loop time. These two features help reducing the average LO power consumption by minimizing the closed-loop frequency calibration time. The duty cycle of the closed-loop time can also be adjusted flexibly to further reduce the average LO power consumption at a given frequency stability requirement. Fabricated in 40-nm CMOS, this proposed algorithm reduces the frequency calibration time from 108 μs to 42 μs, achieving a time reduction of 61%. An average LO power consumption of 93 μW at a 5% closed-loop time duty cycle is measured with a frequency accuracy of 120 ppm.

3D TLC NAND flash memory achieves high storage density due to multi-bit technology and vertical stacked structure, while suffering from severe reliability issues, particularly a high raw bit error rate (RBER). Accurate prediction of RBER in 3D TLC NAND flash memory enables proactive data management, thereby enhancing performance, improving reliability, and extending the lifetime of the memory. This paper focuses on accurately estimating the RBER of flash memory to provide more detailed information for the precise control and optimization strategies. In this paper, we propose a Hybrid Neural Network model (HNN) for RBER prediction, which combines the advantages of multi-layer perceptron (MLP) and recurrent neural network (RNN). The model utilizes a multi-layer perceptron (MLP) for static feature extraction and the gated recurrent unit (GRU) for time series analysis. By combining these approaches, the HNN can effectively capture the complex relationships and temporal patterns that affect the RBER. Experimental results, based on actual chip data, demonstrate that the HNN can predict the RBER with an r-squared value greater than 0.96, significantly outperforming traditional machine learning algorithms and neural networks.

With the development of flash technology, the increasing throughput gap betweennandflash memory (NFM) arrays and the I/O interface has become a performance bottleneck for NFM-based solid-state drives (SSDs). Multilevel parallelism techniques have been employed on modern SSDs to meet the challenge of increasing demands for bandwidth in I/O-intensive workloads. However, conventional parallel methods only monitor the status of ways, resulting in the “idle bubble”—idle time of the dies cannot execute subsequent operations until all the dies in the way complete command execution. This issue limits the resource utilization and performance of SSDs. To minimize the idle bubble, we propose priority-based out-of-order scheduling and fine-grain status polling (POFGSP). The priority-based out-of-order scheduling relaxes constraints on command execution order and schedules commands with the same execution time to be executed in parallel. Therefore, the scheduler reduces these idle bubbles caused by differences in command execution times. Moreover, the fine-grain status polling approach polls the die-level status during the interface’s idle time, reducing idle bubbles with accurate status. Compared to state-of-the-art schedulers, our POFGSP approach can reduce request response time by 35.6% under real-world cloud block storage workloads and improve the SSD system’s maximum bandwidth by 8.7%–74.9%.

Quad-level cell (QLC) has received significant attention recently due to its extremely high storage capacity. However, because of its poor reliability, QLC-based solid-state drives (SSDs) require a two-step programming to reduce the layer interference. But during the interval between two programming steps on the same wordline (WL), data could be invalidated from update operations, leading to invalid programming and degraded performance. To mitigate the performance loss, we propose the NV-APP scheme to minimize the program and verify pulses during the second-step programming. NV-APP integrates the no-verify (NV) scheme and the adaptive pulse programming scheme (APP). The NV scheme omits verify pulses of invalid verify voltages. The APP scheme adaptively increases the programming step voltage$(V_{\mathrm { step}})$to accelerate cells’ threshold voltage shift, reducing the number of both program and verify pulses. Device-level simulation results show that the NV-APP scheme reduces the total number of program pulses by an average of 27.03% and verify pulses by an average of 48.70% across various invalid cases during the second-step programming. Based on a modified 3-D QLC SSD simulator with typical traces, the experiments demonstrate that our scheme reduces two-step programming time by an average of 17% on partially invalid WLs, close to the 19.8% reduction achieved by the ideal scheme with no performance loss.

Progressive low-density parity check (LDPC) code decoding has been widely used to correct increasing raw bit errors in NAND Flash memory. Once the decoding of a single logical page fails, the read-retry operation will reprocess at an increased read level with more accurate initial log-likelihood ratio (LLR) messages. However, the traditional progressive LDPC decodings with inappropriate read-level-increase granularities of read-retry operations introduce unnecessary flash read latency. By taking advantage of globally coupled LDPC (GC-LDPC) codes, an improved adaptive granularity progressive LDPC decoding (IAGPD) is proposed. This method can estimate the number of uncorrectable bit errors before each read-retry operation by detecting the unsatisfied local parity checks and general syndrome in the decoding failure. Then, it adaptively selects the optimal read-level-increase granularities for read-retry operations in the progressive LDPC decoding. Compared with the existing decoding methods, only by an extra 0.098% of the decoder area and two clock cycles, our method can reduce the flash read latency by up to 43%. And the solid-state drive (SSD) read response time on MQsim can be reduced by up to 32%.

Triple-level cell NAND flash memory is widely used today due to its higher storage density and capacity. However, with the increase in the storage density, lower reliability results in more read times for flash memory and significantly reduces the read performance. In order to avoid unnecessary read operations, this article proposes a hard decision–soft decoding method called location information-assisted decoding (LIAD) method, which determines the additional information required for decoding by mutual information, and then transmits the required information to correct the log-likelihood ratio (LLR). Different from the conventional LLR correction algorithm, this method does not require additional read operations and correct data. Only using sensing results, our method can reduce uncorrectable error bit rate (UBER) by up to 99%, and the system read latency under SSDsim (Hu et al. 2011) simulation can be reduced by up to 53%.

Although NAND flash memory does a lot of work in effectively using error correcting code (ECC) to reduce uncorrectable bit error rate (UBER). However, if the frame error rate (FER) is not reduced, the lower UBER cannot effectively reduce the read latency of the flash memory system. This phenomenon is especially evident at the end of the flash memory lifetime, where conventional methods significantly reduce the UBER but not to zero, and the remaining error bits are still evenly distributed throughout the flash memory page, resulting in a significant increase in read latency. In this article, an interleaved LDPC decoding scheme is proposed. By re-evaluating the flash memory channel during the decoding process, the codewords in the flash memory page are corrected frame by frame, and the problem of high FER is solved at the end of the flash memory lifetime. Compared with the conventional algorithm, the proposed method can reduce the FER by up to 34%, reduce the average decoding iterations by 63.4%, and reduce the read latency by up to 65%.

This article presents a small ripple and high-efficiency wordline (WL) voltage generator to supply voltage to the selected/unselected WLs for program and read operation in 3-D NAND Flash memories. With the proposed scheme of dynamic pump clock voltage and frequency scaling, the output ripple voltage can be minimized to reduce the variation of threshold voltage of the memory cells and the efficiency can be improved to save power consumption at the same time. What is more, with the minimized ripple, the requirement for power supply rejection ratio (PSRR) of the high-voltage regulator used to provide low noise WL voltage can be reduced. The proposed WL voltage generator has been fabricated in a 0.18-$\mu \text{m}$triple-well CMOS process and the core chip size is 0.53 mm2. While operating at a 1.8-V supply, the measurement results show that the ripple voltage is 5.5 mV at 12-V output voltage under the typical 50-pF cap load conditions of 3-D NAND Flash memories. Furthermore, the output ripple hardly varies with the increase of load current. In addition, the maximum power efficiency is 49% at 400$\mu \text{A}$and can be maintained over 30% in the 50–450-$\mu \text{A}$current load range.