Pursuit of energy efficiency and accuracy in intelligent edge devices drives emerging non-volatile memories (NVM) developing more advanced computing-in-memory (CIM) architectures. The application of high performance magnetoresistive random-access memory (MRAM) in CIM has been limited due to its inherent non-ideal characteristics such as low resistance, low switching ratio, high area overhead and low accuracy. In this work, we introduce an innovative weighted two-transistor-one-MTJ (W-2T1R) VC-SOT-MRAM CIM macro that addresses these challenges with: 1) a novel 2T1R cell with high TMR; 2) an excellent approach to assign multi-bit array weight and the redundancy sub-track for linear promotion; 3) a bitwise input sparsity dataflow and architecture to improve energy and latency. Our proposal, excels at high linear computing, with energy efficiencies of 105.5 TOPS/W, area efficiency of 0.73 TOPS/mm2, throughput of 7.2 TOPS and classification accuracy of 91.46% on CIFAR-10 dataset for configurations comprising 6-bit input, 3-bit weight and 6-bit output on VGG-8 model.

The combination of computing-in-memory (CIM) architecture and emerging non-volatile memory (NVM) is considered as a promising alternative for low-power electronics. Among different emerging NVMs, the insufficient conductance level of magnetoresistive random-access memory (MRAM) is a serious limitation to introduce its high performance into analogue CIM architecture. In this paper, we propose a probabilistic binary neural networks(PBNN) hardware based on voltage-controlled spin-orbit torque MRAM (VC-SOT-MRAM), which employs 2T2MTJ sub-tracks integrated of the probabilistic switching MTJs to achieve the bit-wise weights sampling and activation. Selective writing is discussed to co-optimized. A pipeline readout circuit with hybrid dynamic reference was suggested to improve the precision and throughput. In addition, a weight mapping method is applied for multi-tracks computing in parallel and kernel duplicating to improve the efficiency. Our proposal, simulated in 28 nm technology, achievean energy efficiency of 312.5 bTOPS/W, throughput of 527.3 bGOPS, accuracies of >90% on MNIST with more acceleration (58×), less resource requirement (32×) and high robust row-parallel computing.