This paper presents a novel class H audio amplifier design that allows full class H operating region, optimizing the efficiency of the class H audio amplifier architecture. Class H audio amplifier is a class AB amplifier, with supply continuously tracks the output voltage, gaining the linearity and power supply rejection ratio (PSRR) performance of the class AB amplifier with much higher efficiency. In prior works on class H audio amplifier architecture, the supply tracking capability has always been limited by the minimum supply requirement for the class AB amplifier to operate. A novel class AB amplifier circuit with bootstrapping architecture to overcome this limitation will be introduced in this paper. The proposed class H audio amplifier is designed and fabricated in GF 55nm BCDLite process, occupying 2.01mm2 total chip area. The proposed class H audio amplifier is able to deliver 186.8mW peak output power to$16\Omega $audio load, while consuming 4.9mW quiescent power. It achieves the lowest A-weighted THD+N of −82dB and −81.5dB at 1kHz and 20kHz, respectively. The proposed class H audio amplifier also achieves 85.1% peak power efficiency, the highest as compared to prior works on class G and class H audio amplifiers. Furthermore, it is also shown in this paper that the efficiency at lower output power is significantly improved with the proposed class H audio amplifier architecture, making it highly suitable for audio applications with high crest factor (peak-to-average power ratio).

This paper presents an improvement on the RF-DC rectifier with the self-bias diode-connected MOS transistors to achieve a wide input power range. The proposed design utilized a dual voltage polarity to bias the rectifying PMOS and NMOS with a positive and negative DC potential respectively. This biasing potential enables the gate of the transistor to be boosted above the output voltage or below the rectifier ground to minimize the leakage current. A proposed 3-stage rectifier design is simulated using a 55nm BCD technology and occupies an area of 0.064 mm2. The post-layout simulation results show a 75.3% power conversion efficiency (PCE) at -7dBm, -22.5dBm sensitivity and an input power range of 21.2dB when operating at the 900MHz input RF frequency with a 100k0 load.

The low voltage low power output-capacitorless (OCL) low dropout regulator (LDO) with embedded voltage reference (EVR) with adjustable and programmable output voltage is proposed in this paper. With the proposed design, the embedded voltage reference (EVR) LDO can provide desired output voltages of 435mV, 500mV, 550mV, and 600mV in single LDO design. The dropout voltage is 60mV for low power consumption. The proposed circuit is implemented and simulated in 55nm CMOS technology. The circuit consumes 30μA of quiescent current and 0.0234mm2chip area. Simulation results show that the line regulation is below 12.5mV/V, load regulation is below 2.6mV/mA and temperature coefficient (TC) is below 59ppm/oC under all different output voltage modes of the LDO. Stability of the proposed design is also verified in simulation. The design also has fast transient recovery time of less than 1.67μs under 100ns rise/fall time load current transient.