This paper presents the OpenRAN@Brasil testbed, designed to address the challenges of Open RAN deployments in Brazil. It is composed by commercial off-the-shelf 5G Open RAN components, distributed over two sites, and interconnected by a 400 km midhaul link. We use this to evaluate end-to-end network performance (latency and throughput) under diverse signal conditions. Results show that the long-haul link increases latency to up to 28 ms, degrading downlink throughput by up to 400 Mbps, while the lower uplink throughput is less affected. These findings highlight the importance of strategic RAN component placement and robust signal quality for optimizing Open RAN performance in challenging environments, particularly within the Brazilian ecosystem.

A testbed with open-source tools and commercial equipment is designed to investigate the timing of ML-based xApp operations in DDoS attack detection during the Random Access procedure. Results show high-precision and high-recall ML classifiers operating faster than the Medium Access Control (MAC) layer's Contention Resolution timer. For classifiers with over 97% precision and recall, XGBoost has the fastest execution time and the narrowest estimated run time probability density function.

Despite having received less attention compared to the control and application plane aspects of software-defined networking (SDN), the data plane is a critical piece of the puzzle. P4 takes SDN datapaths to the next level by unlocking deep programmability through a target-independent high-level programming language that can be compiled to run on a variety of targets (e.g., ASIC, FPGA, and GPU). This paper presents the design and evaluation of our sweet spot approach on SDN datapaths, offering three contending characteristics, namely, performance, portability, and scalability in multiple realistic scenarios. The focus is on our Multi-Architecture Compiler System for Abstract Data Planes proposal, which blends the high-level protocol-independent programmability of P4 with low-level but cross-platform (HW & SW) Application Programming Interfaces brought by OpenDataPlane, this way supporting many different vendors and architectures. Besides the performance evaluation for varying packet sizes and memory lookup tables, we investigate the impact of increasing pipeline complexity ranging from elemental L2 switching to more complex data center and border network gateways. We investigate the scalability for increasing the number of cores and evaluate a novel method for run-time core reallocation. Furthermore, we run experiments on different target platforms (e.g., ×86, ARM, 10G/100G), inducing different ways of packet mangling through specific drivers (e.g., DPDK and Netmap), and compare the results to state-of-the-art datapath alternatives.