The decomposition-based chiplet design paradigm, which breaks monolithic system-on-chips (SoCs) into smaller chiplets, has proven effective in reducing costs and accelerating development. The vast design space of multi-chiplet systems necessitates automated techniques to maximize their benefits while minimizing overheads. However, current chiplet decomposition flows lack support for exploring reusable chiplets, missing opportunities to efficiently amortize non-recurring engineering costs. To fully unleash the economic potential of chiplets, we propose CHIPLETIZER 2.0, a cost-driven framework that guides SoC decomposition and enables chiplet reuse across a line of products. This early-stage chiplet planning framework determines critical system parameters involving the partition, floorplan, and D2D interface, based on user-specified optimization goals. Experimental results demonstrate that, compared with the existing chiplet decomposition techniques, our proposed framework achieves significant cost improvements on realistic product lines with acceptable overheads.

With the slowdown of Moore’s Law, conventional monolithic chip architectures face challenges such as excessive die sizes and prohibitive manufacturing costs. Consequently, chiplets have emerged as a pivotal technology in the post-Moore era, attracting significant attention from both academia and industry. Multi-chiplet systems offer compelling advantages over monolithic ones, including enhanced integration density, reduced cost, and shortened time-to-market. However, realizing these benefits necessitates design flows capable of optimizing parameters across logical, physical, and circuit layers, which introduces substantial design complexity. Numerous design automation technologies have been proposed to address these challenges. This article provides a comprehensive overview of related advancements, categorizing chiplet design methodologies into two primary types: (i) top-down flows disintegrating existing hardware designs into chiplets and subsequently reintegrating them into multi-chiplet systems, and (ii) bottom-up flows combining existing chiplets into multi-chiplet systems based on user applications. This article begins by introducing foundational concepts, technical characteristics, and evaluation models relevant to multi-chiplet systems. We then systematically summarize the problem formulations, design spaces, and optimization techniques associated with top-down and bottom-up design flows. Finally, we discuss key challenges and potential future research directions in chiplet design automation, aimed at further harnessing the potential of chiplet-based integration.

Accurate occupancy counting is essential for effective space management, safety protocols, and resource optimisation in various environments. In recent years, the rapid development of the Internet of Things (IoT) has advanced traditional WiFi sensing into a new domain of research known as Integrated Sensing and Communication (ISAC). Such technology enables simultaneous communication and sensing, allowing for efficient data transmission while gathering environmental information. In this paper, we conduct a novel experimental demonstration and robustness validation of ISAC for occupancy counting. Compared to traditional WiFi sensing technology, we first demonstrated that human presence can be detected by sensing applications using communication packets. Specifically, using our Machine Learning (ML) algorithm, we got a sensing accuracy of more than 96 %. However, we found that this accuracy decreases with increased communication rates and higher occupancy levels, as they introduce noise and interference into the WiFi channel. We also experimentally investigated edge communication, which reveals a tradeoff between occupancy monitoring and communication rate regarding the number of Transmission Control Protocol (TCP) retransmission requests for different distances. We observed that improved accuracy results in an increase in TCP retransmission requests and a reduced communication quantity. Both sensing and communication performance lie in an optimal deployment of the transmit and receive with devices. Further tests at various distances revealed novel insight that sensing performance is better at both short and long distances. Specifically, we present that sensing benefits from diverse reflections, whereas communication relies on a balance best achieved at intermediate distances.

As the number of chiplets in 2.5D IC continues to increase, existing chiplet placement method faces two main challenges: (1) the combinatorial explosion in the search space, and (2) the difficulty of achieving global optimization through iterativing chiplet and terminal placement. To tackle these challenges, we develop an efficient analytical RDL chiplet-terminal co-placement algorithm, to ensure simultaneous placement of chiplets and terminals. Our algorithm employs RDL chiplet-terminal co-placement in three stages: analytical global placement, legalization, and bump-terminal assignment, to achieve high-quality placement results that comply with design rules. Experimental results demonstrate that our algorithm reduces average wirelength by 31% compared to prior work for the common testcases, with a maximum speedup of up to 6500× in testcases with more than 10 chiplets.