This paper proposes FPN-ResUNet, which uses feature points-based restoration and nonlinear decay rate residual within a U-shape architecture to restore blurry and wet fingerprints within size constraints effectively. Our approach aims to restore fingerprints effectively while avoiding over-restoration and preserving local matching feature points, which reduces the false rejection rate (FRR). We develop novel residual blocks, which feature a nonlinear decay mechanism that optimizes weight allocation between blocks to enhance feature extraction capabilities. Furthermore, our residual feature points fusion module restores contextual information by fusing matching feature points and features from the previous level.Through comprehensive experiments on real-world data, we achieved a remarkable 9.4% reduction in FRR. Our method outperforms the basic U-Net framework [1] by 50.52% in overall performance. We improved 48.35% over FPDMNet [2] and 58.77% over DenseUNet [3] which is trained with small patches. Moreover, PGT-Net [4] is also used for small areas of wet fingerprints, but our FPNResUNet outperformed it by 72.51%.

Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests for single stuck-at faults. DR-scan is able to test memory elements in dual-rail logic without breaking local feedback loops. To reduce test time, we choose a minimum set of selected test configurations (TCs). If there are more than one selected TCs, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our test methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve test coverage up to nearly 94% for various asynchronous circuits.

Among many asynchronous design styles, precharge half/full buffers (PCHB/PCFB) are popular due to small area and high performance. This paper proposes new test methodology for PCHB/PCFB asynchronous circuits. Our proposed design for testability (DfT) does not break any internal feedback loop so it is small in area. There are two major theoretical contributions in this paper. First, this paper analyzes the fault effects of transition delay faults, which were not studied in depth by previous research. Second, we also analyze faults on fanout branches that break the isochronic fork assumption. One important conclusion is that these faults can not only degrade the circuit performance but also modify data so they must be tested. We propose three-pattern tests for stuck-at faults and four-pattern tests for transition delay faults. In addition, we propose a new model for ATPG so that existing tools can be used. On the average, our work achieves 93% and 92% stuck-at and transition delay fault coverage, respectively, which is much higher than previous techniques.