Haptic interfaces enable shape simulation in virtual reality, making such content "tangible". Among existing haptic technologies, "grounded" interfaces simulate convincing grounded surfaces (like walls, tables, or other grounded shapes) but have limited workspaces, while "portable" interfaces are usable everywhere but struggle to display force feedback. In this paper, we formalize an alternative approach that we call "anchor-based haptics", which consists of portable interfaces capable of temporarily making contact with a real surface and leveraging it for grounded force feedback. To illustrate this approach, we present two new interfaces: T-Hank, which uses a reel-based extension mechanism to give height feedback from the surface, and R-Hank, which provides orientation feedback. The design of these interfaces is presented, and their potential interest in virtual reality has been investigated within two user studies by comparing them with vibrations in various 3D tasks. Overall, T-Hank and R-Hank enhance user experience for the exploration of 3D shapes and softness sensations. Taken together, results promote the use of the anchor-based haptic approach for VR applications in which both a large workspace and shape simulation play a prominent role.

Many emerging non-volatile memories are compatible with CMOS logic, potentially enabling their integration into a CPU’s die. This article investigates such monolithically integrated CPU–main memory chips. We exploit non-volatile memories employing 3D crosspoint subarrays, such as resistive RAM (ReRAM), and integrate them over the CPU’s last-level cache (LLC). The regular structure of cache arrays enables co-design of the LLC and ReRAM main memory for area efficiency. We also develop a streamlined LLC/main memory interface that employs a single shared internal interconnect for both the cache and main memory arrays, and uses a unified controller to service both LLC and main memory requests. We apply our monolithic design ideas to a many-core CPU by integrating 3D ReRAM over each core’s LLC slice. We find that co-design of the LLC and ReRAM saves 27% of the total LLC–main memory area at the expense of slight increases in delay and energy. The streamlined LLC/main memory interface saves an additional 12% in area. Our simulation results show monolithic integration of CPU and main memory improves performance by 5.3× and 1.7× over HBM2 DRAM for several graph and streaming kernels, respectively. It also reduces the memory system’s energy by 6.0× and 1.7×, respectively. Moreover, we show that the area savings of co-design permits the CPU to have 23% more cores and main memory, and that streamlining the LLC/main memory interface incurs a small 4% performance penalty.