This paper presents a low-power supply-to-digital converter (SDC) for bio-recording system where bio-fuel-cell provides both power and sensing data. It is achieved by a supply-controlled oscillator, supply-dependent activation buffers (SDAB) with different V-thresholds, and an encoder. A 22-nm prototype chip exhibits its feasibility with a power of 0.9-2.6 pW under 0.1-0.25 V. Design methodology for minimizing power consumption and techniques of controlling buffer V-threshold are also introduced.

The demand for high energy efficiency in IoT devices continues to increase, necessitating the development of low energy consumption techniques to enhance the computation performance of these devices. In this study, we present a CMOS clock generator that operates at high operating voltage, achieves low frequency, and exhibits low power (LP) consumption, thus obviating the need for scaling-unfriendly step-down converters. The avoidance of step-down converters, which require passive components in their design, facilitates the development of scaling-friendly IoTs. The architecture of the prototype chip is composed of a voltage stacking and charge recycling design, which is achieved by the implementation of stacked oscillator and multiple frequency dividers in a configuration. The fabrication of the prototype chip is conducted using a 65-nm CMOS process. This work presents two configurations that are based on the concept of voltage stacking. The first configuration prioritizes LP consumption, yielding a clock generation of 2.09 Hz with a power of 0.22 nW at a voltage supply of 1.2 V and an operating range of 1.2–2.2 V. Notably, this configuration represents the lowest power achieved at a foundry-recommended nominal voltage in a sub-10-Hz clock generator. Another configuration is oriented toward generating low-frequency output signals, and the test chip attains an output frequency of 0.079 Hz and a supply voltage range of 0.88–1.3 V. The proposed architecture exhibits potential benefits in advanced technology nodes, particularly in the context of technology scaling.

True random number generators (TRNGs) are commonly used in hardware security for secure authentication, data encryption, etc. The raw random numbers often exhibit defects. The most commonly observed defects are bias and correlations. Post processing techniques have been developed to address them. The von Neumann method addresses bias, but it requires input that is uncorrelated and has an identical distribution. On the other hand, the Markov chain can address correlation but introduce bias. In this work, we research the lightweight combination of two techniques. We verified that MKV2(QL4)/VN2 performs well for both Markov and non-Markov model bitstreams. MKV1(QL8)/VN8W is effective for the Markov model. The randomness is verified by NIST SP 800-22 and 800-90B, and ENT, respectively. Both of these circuits require only 16 bits of memory, which is 12 times smaller than in previous work. MKV1(QL8)/VN8W is implemented using 65-nm CMOS. A prototype chip demonstrates a minimum energy consumption of 0.149 pJ/bit at 0.45V. When applied to a latch-based TRNG, it can double the operation frequency thanks to the enhanced decorrelation. The total energy consumption is reduced by 21%.

This article presents a true random number generator (TRNG) that achieves high entropy generation across wide voltage and temperature (VT) range (0.3–1.0 V, −40 °C to 110 °C) in a single latch-based entropy source (ES). In the ES, static inverter selection technique to minimize the mismatch between the paired inverters, and noise enhancement methods to increase the root mean square (rms) of noise voltage ($\sigma _{n}$) are implemented for good randomness and robustness. In a 130-nm CMOS technology, the TRNG occupies 5343$\mu \text{m} ^{\mathrm{ 2}}$and consumes 0.116 pJ/bit at 0.3 V including an on-chip von Neumann post-processing circuit. The cryptographic quality of TRNG’s output is verified by National Institute of Standards and Technology (NIST) SP800-22 tests. Up to 325 mV$V$pp noise injection attack tolerance is confirmed by power supply frequency injection attack. And an equivalent 20-year life at 0.3 V, 25 °C is verified by accelerated NBTI aging test.