Recent advancements have marked significant progress in photoacoustic imaging as an effective method for acquiring deep bio-tissue visuals in modern medical clinical therapy and the efficacy of U-Net and its variants has been established for imaging quality enhancement in this field. Unlike common computer vision datasets such as ImageNet [1] and PASCAL VOC [2], biomedical images exhibit highly structured patterns, low spatial resolution, and single-channel modality, as shown in Fig. 1. Additionally, the U-Net parameters trained for medical super-resolution tasks demonstrate a high sparsity ratio, making them suitable for implementation on edge-computing platforms. Therefore, developing an energy-efficient photoacoustic imaging setup in this area is a natural progression. However, this development is constrained by the current neural network architectures, which are built around a U-Net backbone. The multi-stage feature extractor, skip connection integration across different blocks, and the encoder-decoder backbone design pose significant challenges to cutting-edge computational hardware platforms. In this study, a scalable, sparsity-supported neural network accelerator architecture for bio-tissue imaging quality enhancement is proposed to meet the stringent requirements of latency and energy efficiency, as depicted in Fig. 2. This architecture achieves desired performance improvements by exploring the sparsity possibilities in neural network during the training process and implementing an end-to-end pixel-first hardware design to minimize data movement and support sparsity computation. Compared with the state-of-the-art related works, this optimized architecture has achieved minimum on-chip storage overhead and the fastest frame for the application of photoacoustic imaging quality enhancement. The scalable architecture has also been implemented on a Xilinx XCZU9EG FPGA and attains a performance of PSNR@ 24 dB and a frame rate of 164 fps at a working frequency of 250 MHz.

In this work, a solid-state direct time-of-flight (dToF) and adaptive beam-steering Light Detection and Ranging (LiDAR) system is proposed for machine learning (ML) based object detection. To leverage the capabilities of software and hardware, a co-optimization design from a neural network based algorithm to the architecture of transmitter, receiver and optical components is realized. Firstly, an object detection neural network is proposed for the depth-only input algorithm, which indicates the Region of Interest (ROI) in the illuminating field and gives hints of opened scan channels in the next two frames to decrease the total cost of the laser driver and sensor array. Next, the proposed network utilizes the Cross-Stage-Patrial (CSP) block to replace the residual structure in the backbone to achieve a lightweight performance and is implemented on the NVIDIA-Jetson to verify the system-level adaptive beam steering feature. To realize the smart working mode, a customized multi-channel and addressable TX is designed for adaptive and optical control to save power consumption and extend the ranging distance. At the same time, a 128×80 resolution RX which consists of Single-Photon Avalanche Diodes (SPADs) and column-wise Time-to-Digital Converter (TDC) is incorporated to capture the returned photons for combining sub-regions into an entire depth map. Next, to customize the specific scanning mechanism, for the optical setup, a cylindrical lens array is designed to reshape the laser beam, which matches the pattern of the transmitter to illuminate different targeted objects. Both the laser driver chip and the sensor chip with a 128×80 SPAD array are fabricated in the 180-nm Bipolar-CMOS-DMOS (BCD) process. Finally, the laser driver chip realizes the power of 5 W with an adjustable pulse width of 1.5 ns and the SPAD array integrates the depth accuracy of 5 cm at 15 m. Due to that the neural network realizes an accuracy up to 0.8, a low-power solid-state LiDAR prototype with adaptive beam steering is demonstrated.

This paper presents a high-speed and high-resolution On-Chip Oscilloscope (OCO) for Auto-Peak-Power Controller (APPC) and Peak-Current Detector in voltage mode Direct Time-of-Flight(DToF) driver. The OCO supports both optical input and electrical input, with front-end circuit of TIA and PGA respectively. The front-end circuit bandwidth is up to 2GHz to support 500ps pulse width detection. The optical input is for detecting VCSEL peak power, and feedback to the integrated Boost Converter to adjust VCSEL supply voltage to find the target peak optical power. The electrical input is for detecting the VCSEL peak current to avoid driver over-current, by preventing APPC from adapting to excessive peak current due to abnormal VCSEL or PD. The front-end circuit is followed by an 11-bit asynchronous logic SAR-ADC with up to 40MHz sampling rate. The OSC time accuracy is 6.6ps and detected pulse width is up to 12.8ns. The chip was fabricated in BCD180nm process. According to the test results, the measured waveform of OCO is comparable with commercial oscilloscope. By turning on the OCO-based APPC feature, the variation of optical power is controlled within 3% in the temperature range of 25-85°C.

This paper presents an angle-insensitive light sensor by means of two pairs of Dual-Photodiodes (PDs) for X-axis and Y-axis direction respectively. A time-interleaved architecture is proposed to support 4-Channels (CHs) simultaneous flicker detection, sharing two Trans-Impedance-Amplifiers (TIAs) and one 16-bit third-order incremental Δ∑ADC. 7-Levels Auto-Gain-Control (AGC) is implemented to extend dynamic range and Dark-PD is introduced to track and cancel temperature-dependent offset. The chip was fabricated using 180nm CMOS technology. Test results show that the proposed light sensor achieves −30°∼30° flat angular response with +/−67° field-of-view (FOV). AGC extends input dynamic range to 138dB(0.012∼103klux), with linearity error of 0.169%. Up to 610Hz 4-Channels flicker can be detected in parallel at 0.053lux light input. Dark offset variation is controlled within +/−1.2LSB in the range of −30°C∼85°C. The chip draws 212uA from 1.8V supply and chip area is$2\text{mm}\times 0.65\text{mn}$.

Silicon photodetectors, such as photodiode (PD), are extensively used in optical sensing as their proper performance and low cost to achieve screen brightness adjustment, ambient light flicker detection, and other functions. With the rise of under-screen optical sensing, PD is no longer sufficient for low-light level light detection and real-time low light level flicker detection. While an emerging detector, single photon avalanche diode (SPAD), shows its advantage to ultralow light sensing. However, SPAD tends to saturate at high light levels, which limits its widespread application. To inspire ambient light sensor design and address these issues, this paper proposes a high sample per second (SPS), wide dynamic range (DR) and ultralow illuminance detection SPAD array system on chip (SoC). A$16\times 16$SPAD array architecture along with counter and charge-pump is designed in 180nm BCD process to sense 100μdux ambient light at 660nm. On-chip FFT processor of 2048 points with 32-bit accuracy is realized to process sampled optical waveform for flicker detection. Besides, an area-efficient integrated charge pump is implemented to regulate high-voltage (19~25V) to SPADs with on-chip digital auto-gain control (AGC), which improves the optical DR from 87db to 123db. This work extends the optical sensing range significantly and demonstrates the effectiveness of the proposed SoC with systematical measurements.

This paper demonstrates a ranging sensor system with a configurable array of$16 \times 16$single photon avalanche diodes (SPADs), a 940nm vertical cavity surface-emitting laser (VCSEL), a co-design VCSEL driver with tunable widths from 400ps to 3630ps full-width at half-maximum (FWHM) optical pulses and peak power from 30mW to 170mW, and an embedded core to implement adaptive optical power control and distance extraction. An adaptive optical power control and a shifted bins binning of the histogram (SBbH) method to achieve high-precision distance measurement both at short-range and long-range. We achieved a minimum distance of 20mm with an absolute error better than 20% (4mm), still with a precision better than 10mm at 7m. All of results are obtained with 80% reflectivity of target at 100 frame rate.

This paper presents an integrated pulsed laser driver in 180nm BCD process for indirect time-of-flight applications. Pulses with 4A peak current at a modulation frequency up to 200MHz can be generated. Automatic optical power control (AOPC) is realized for laser eye safety protection. A DLL-based time interpolator is proposed to eliminate the mechanical moving components used during system calibration. The measured absolute accuracy of the time interpolator is +/−50ps with a resolution of 800ps and tuning range of 49. 6ns. This work effectively extends the measurement distance of the I-ToF system. The calibration efficiency is also improved with the proposed method.