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Weihang Shen

dblp:232/7538 · DBLP profile ↗
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3ranked-venue papers
1as first author
3since 2021 · last 2026
0009-0007-2568-177XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
GPUs and heterogeneous computing · 47% Distributed systems · 16% Parallel and multicore computing · 14%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Distributed systems › fault tolerance
checkpointing
1.012026
Accurate and Ultra-Fast Launch-Time Validation of Idempotency for GPU Kernels · EuroSys 2026
GPUs and heterogeneous computing › GPU scheduling
concurrent kernel execution
1.012026
Real-time, Work-conserving GPU Scheduling for Concurrent DNN Inference · ACM Trans. Comput. Syst. 2026
GPUs and heterogeneous computing
GPU kernel
1.012026
Accurate and Ultra-Fast Launch-Time Validation of Idempotency for GPU Kernels · EuroSys 2026
GPUs and heterogeneous computing
GPU scheduling
1.012026
Real-time, Work-conserving GPU Scheduling for Concurrent DNN Inference · ACM Trans. Comput. Syst. 2026
Parallel and multicore computing › parallel scheduling
heterogeneous scheduling
0.912025
XSched: Preemptive Scheduling for Diverse XPUs · OSDI 2025
Embedded and real-time systems › real-time scheduling
preemptive scheduling
0.912025
XSched: Preemptive Scheduling for Diverse XPUs · OSDI 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference
DNN inference serving
0.312026
Real-time, Work-conserving GPU Scheduling for Concurrent DNN Inference · ACM Trans. Comput. Syst. 2026
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.312026
Real-time, Work-conserving GPU Scheduling for Concurrent DNN Inference · ACM Trans. Comput. Syst. 2026
Operating systems › resource management › process management
CPU scheduling
0.312025
XSched: Preemptive Scheduling for Diverse XPUs · OSDI 2025

Methods — techniques the papers use, named apart from their topics

kernel preemption · 1.0dynamic kernel padding · 1.0
YearPublicationVenuePosition
2026 Accurate and Ultra-Fast Launch-Time Validation of Idempotency for GPU Kernels
abstract
We discovered that a GPU kernel can have both idempotent and non-idempotent instances depending on the input. These kernels, called conditionally-idempotent, are common in real-world GPU applications—490 out of 547 from six popular applications. This finding reveals a limitation in previous work that statically classifies GPU kernels as idempotent or non-idempotent, potentially compromising the correctness and effectiveness of idempotence-based systems. This paper presents Picker, the first launch-time analysis system for instance-level idempotency validation. Picker accurately validates the idempotency of GPU kernel instances before execution by utilizing launch arguments. Several optimizations are proposed to reduce validation latency to microseconds. Evaluations using representative GPU applications (547 kernels and 18,217 instances) show that Picker accurately identifies idempotent instances with zero false positives and an 18.54% false-negative rate. The launch-time validation completes in under 5 μs for all instances (about 90% under 1 μs). Through integration, Picker reduces checkpoint costs to less than 4% in fault-tolerant systems and decreases preemption latency by 84.2% in scheduling systems.
Mingcong Han, Weihang Shen, Rong Chen 0001, Haibo Chen 0001
EuroSys2
2026 Real-time, Work-conserving GPU Scheduling for Concurrent DNN Inference
abstract
Many intelligent applications, such as autonomous driving and virtual reality, require running both latency-critical (real-time) and best-effort deep neural network (DNN) inference tasks to achieve both real-time and work-conserving on the GPU. However, commodity GPUs lack efficient preemptive scheduling support, and existing state-of-the-art approaches either have to monopolize GPU or let real-time tasks to wait for best-effort tasks to complete, resulting in low utilization, high latency, or both. This article presents Reef , the first GPU-accelerated DNN inference serving system that achieves low-latency and work-conserving for concurrent real-time and best-effort tasks. Reef accomplishes this by enabling microsecond-scale kernel preemption and controlled concurrent execution in GPU scheduling. Reef is novel in two ways. First, based on the observation that DNN inference kernels are mostly idempotent, Reef devises a reset-based preemption scheme that launches a real-time kernel on the GPU by proactively killing and restoring best-effort kernels at microsecond-scale. Second, since DNN inference kernels have varied parallelism and predictable latency, Reef proposes a dynamic kernel padding mechanism that dynamically pads the real-time kernel with appropriate best-effort kernels to fully utilize the GPU with negligible overhead. Evaluation using a new DNN inference serving benchmark (DISB) with diverse workloads and a real-world trace on both NVIDIA and AMD GPUs shows that Reef only incurs less than 5% overhead in end-to-end latency for real-time tasks but increases the overall throughput by up to 1.53×, compared to scheduling tasks sequentially. To demonstrate the practical benefits of our approach, we compare Reef with Triton, a widely-adopted production-level serving system. Our evaluation shows that Reef outperforms Triton by 1.12× to 5.20× in end-to-end latency for real-time tasks, while maintaining comparable throughput.
Mingcong Han, Rong Chen 0001, Weihang Shen, Hanze Zhang, Haibo Chen 0001
ACM Trans. Comput. Syst.3
2025 XSched: Preemptive Scheduling for Diverse XPUs
Weihang Shen, Mingcong Han, Jialong Liu, Rong Chen 0001, Haibo Chen 0001
OSDI1