This paper presents a novel ISFET architecture with in-pixel ADC for large-scale integration and on-chip computational capabilities. Each pixel is composed by a comparator connected to a set of memory elements, storing in-pixel each conversion. Using this sensing scheme, the entire frame of ISFET pixels is acquired and stored in one single ADC cycle, eliminating the need for global or column-level ADCs and making this architecture scalable to larger arrays without instrumentation overhead. To enable compensation of ISFET non-idealities such as trapped charge, a novel gate-bootstrapping mechanism is introduced, enhancing the ADC dynamic range without additional circuitry and accommodating a trapped charge compensation range of 4.45 V. Fabricated in standard 180nm CMOS technology, the system is composed by a 16x16 ISFET array, a global DAC and a Digital Control Unit that enables operation and off-chip communication. The entire frame is acquired in 51.2 μs with a pixel power consumption of 10.15 μW, while storing the result in-pixel and eliminating the need for off-chip memories.

This paper presents a multi-sensing pixel capable of sensing ion concentration, temperature, moisture and light from the same spatial point. The presented pixel is composed of an ISFET chemical sensor, a light sensor, a moisture sensor and a temperature sensor, all implemented in standard CMOS technology in a compact pixel. All sensing modalities are acquired simultaneously and modulated onto a single waveform using multi-frequency PWM modulation, overcoming the associated transmission overhead. Furthermore, ISFET non-idealities such as trapped charge are compensated through a global DAC, balancing the input linear OTA, while the light sensor dark current is mitigated in-pixel by subtracting its influence using a reference photodiode. The proposed pixel occupies 50×50 μm2, and it is integrated as part of a 4×4 multi-sensing array, along with on-chip biasing, instrumentation and digital control. To the best of our knowledge, this architecture represents the first multi- sensing architecture capable of extracting four features from the same spatial point simultaneously, enabling ISFET-based platforms to sense both the chemical signal and the external conditions influencing its measurement.

This paper presents a 4 channel ASIC for sEMG sensing with in-built muscle fatigue and activity feature extraction. Each channel filters and conditions the electrode signal in parallel, while extracting key features for Low Back Pain (LBP) fatigue monitoring and forecasting - Zero Crossing rate and Root Mean Square through sEMG Envelope. The channels are integrated with a Transimpedance Amplifier, an 10-Bit ADC and a Digital Control Unit to digitise and enable transmission of extracted features. Fabricated in TSMC 180nm, these channels present a compact form factor (90μm× 630μm,) and a low power consumption (42.61 μw), ideal characteristic for wearable devices utilised for long-term monitoring of activities.

This paper presents an Ion-to-Frequency ISFET architecture capable of operating at low power supplies, targeting fully-digital ultra-low power applications. The ISFET, biased in weak inversion, encodes the pH concentration as a frequency modulated digital signal by controlling the polarity and discharge rate of a capacitor. This architecture is implemented using digital gates operating at low voltages, achieving minimal power consumption and addressing the need for scalability to deep sub-micron technologies. Implemented in TSMC 0.18μm standard CMOS technology, each pixel occupies 20 μm × 21 μm and consumes a maximum of 33 pW operated at 0.2V while preserving a large sensitivity of 287 Hz/pH at a center frequency of 697Hz. Simulation results indicate low power consumption with a compact pixel size, becoming an efficient solution for the next-gen of portable and wearable applications.

This paper presents a novel 32×32 ISFET array for DNA amplification detection. Each pixel contains a highly-linear ISFET-based OTA and a sawtooth oscillator, converting the solution pH into a digital clock with chemically controlled duty cycle. By employing a differential measurement between a DAC-generated voltage and the pH solution on the OTA, a highly linear, PVT-insensitive response is achieved, while opening the possibility of real-time pixel-wise compensation of trapped charge and chemical drift. The proposed architecture achieves a sensitivity of 11.78%/pH while maintaining large linear dynamic range and a temperature sensitivity of 0.0033 pH/K. Implemented using 0.18μm standard CMOS technology, each pixel occupies 40 μm × 40 μm. This architecture paves the way towards a new generation of ISFET imagers, capable of learning from data and correcting their measurements in real time.