The Internet-of-Things (IoT) devices feature a broad range of power, memory, and performance requirements. Ultralow-power, low-performance controllers are at one end of the spectrum, while high-performance, power-intensive systems-on-chip (SoCs) are at the other. Heterogeneous and specialized multiprocessor SoC (MPSoC) architectures have emerged as the most effective paradigm for delivering high performance and energy efficiency across a wide range of application workloads. This work introducesHeadsail, an MPSoC application-specific integrated circuit (ASIC) designed by SoC Hub at Tampere University, Finland.Headsailfeatures a 512-KiB primary data buffer, 128 KiB of shared on-chip SRAM, seven CPU cores (including four CVA6 64-bit RISC-V processors), a low power-DDR2 (LP-DDR2) memory controller, two unique chip-to-chip (C2C) interfaces, and shared peripherals.Headsailhas been successfully implemented using a TSMC 22-nm low-power CMOS technology. Testing results show that the samples can support a maximum operating frequency of 1 GHz and achieve a peak performance of 1100 giga operations per second (GOPS), with an implementation area of 25 mm2and a power-consumption range of 64 mW–1.5 W.

Context switching is both a highly utilized and highly repetitive routine in interrupt-driven systems, such as safety-critical control systems. Conventional context switching routines are sequential and dependent on data memory access, which may be detrimental to time-predictability. This publication explores the use of stacked register files for efficient and predictable context switching. Two complementary microarchitectures are characterized: combinationally addressed register windowing, and a novel parallel context stack (PCS). Both implementations enable minimal latency and inherent predictability in context switching. To efficiently utilize the benefit of stacked register files while limiting hardware costs, the heterogeneous interrupt (HETI) architecture is proposed. HETI integrates a small stacked register file for accelerating a dynamically selected subset of high-priority interrupts. Automatic firmware generation is contributed to enable seamless utilization of the HETI architecture. A total of four HETI configurations on an open-source RISC-V microcontroller are evaluated against the baseline platform and an implementation of Cortex-M style hardware-assisted stacking. Implementations on a TSMC 22nm technology demonstrate low area overhead for small HETI configurations and favorable frequency characteristics against the hardware-assisted stacking implementation. A representative layout of the full system with a HETI-4 instance is presented with a gate count overhead of 1.2% and no frequency detriment in relation to the baseline design. The functional performance evaluated in a synthetic case study demonstrates how the HETI design can reduce retired instruction count by up to 26% and allow for 21% more sleep in comparison to the software baseline and Cortex-M style solution, promising significant improvements to real-time response and energy efficiency.

The integration of large-scale systems-on-chip warrants thorough verification both at the level of the individual component and at the system level. In this article, we address the automated testing of system-level memory maps. The golden reference is the IEEE 1685/IP-XACT hardware description, which includes implementation agnostic definitions for the global memory map. The IP-XACT description is used as a specification for implementing the registers and memory regions in a register transfer-level (RTL) language, and for implementing the corresponding hardware-dependent software. The challenge is that hardware design changes might not always propagate to firmware and applications developers, which causes errors and faults. We present a method and a tool called Keelhaul which takes as input the CMSIS-SVD format commonly used for firmware development and generates automated software tests that attempt to access all available memory mapped input/output registers. During development of a large-scale research-focused multiprocessor system-on-chip, we ran a total of 32 automatically generated test suites per pipeline comprising 882 test cases for each of its two CPU subsystems. A total of 15 distinct issues were found by the tool in the lead-up to tapeout. Another research-focused SoC was validated posttapeout with 984 test cases generated for each core, resulting in the discovery of four distinct issues. Keelhaul can be used with any IP-XACT or CMSIS-SVD-based systems-on-chip that include processors for accessing implemented registers and memory regions.

This paper presents a highly resilient boot process design for Ballast, a new RISC- V based multiprocessor system-on-chip (SoC). An open source RISC- V SoC was adapted as a bootstrap processor and customized to meet our requirement for guaranteed chip wake-up. We outline the characteristic challenges of implementing a large program into a read-only memory (ROM) used for booting and propose generally applica-ble workflows to verify the boot process for application specific integrated circuit (ASIC) synthesis. We implemented four distinct boot modes. Two modes that load a software bootloader autonomously from an SD card are implemented for a secure digital input output (SDIO) interface and for a serial peripheral interface (SPI), respectively. Another SDIO based mode allows for direct program execution from external memory, while the last mode is based on usage of a RISC- V debug module. The boot process was verified with instruction set simulation, register transfer level simulation, gate-level simulation and field-programmable gate array prototyping. We received the fabricated ASIC samples and were able to successfully boot the chip via all boot modes on our custom circuit board.