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Zois-Gerasimos Tasoulas

dblp:233/0633 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2019
0000-0003-2857-7912ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 30% Memory systems · 30% Parallel and multicore computing · 30%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › shared memory
distributed shared memory
0.412019
A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Processor architecture and microarchitecture
multicore design
0.412019
A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Parallel and multicore computing
synchronization
0.412019
A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019
Hardware accelerators and domain-specific architectures › accelerator architecture
programmable accelerator
0.112019
A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019

Methods — techniques the papers use, named apart from their topics

microcoded synchronization · 0.4client-server synchronization model · 0.4
YearPublicationVenuePosition
2019 A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures
abstract
Implementation of concurrent data structures in architectures that provide limited synchronization primitives is a critical challenge. Typical lock-based implementations suffer from well-known problems such as poor scalability and unfairness. In this paper, we propose a client-server based synchronization model that can be applied in data structures with low level of parallelism for distributed shared memory many-core systems that support also message-passing communication. Additionally, we utilize a programmable hardware accelerator with appropriate application interfaces to overcome the performance-flexibility dilemma. Experimental results show that the proposed work performs 20$\times$ faster than the single lock model with 88$\times$ less idle cycles and 7$\times$ less power consumption.
Zois-Gerasimos Tasoulas, Iraklis Anagnostopoulos, Lazaros Papadopoulos, Dimitrios Soudris
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1