We present Ishtar, a power-efficient RISC-V baseband system-on-chip (SoC) tailored for multi-standard integrated sensing and communications (ISAC) in low-altitude wireless networks (LAWNs). Ishtar integrates a hierarchical scheduling scheme and a system-level power-gating architecture that dynamically controls power domains to balance performance and energy efficiency. It supports dynamic task scheduling across heterogeneous protocols using a domain-specific, graph-based representation. Implemented in 40 nm technology and running at 300 MHz, Ishtar achieves better normalized efficiency than state-of-the-art SDR SoCs, delivering real-time multi-standard sniffing under stringent power and area constraints.

Wireless baseband processing (WBP) is a key element of wireless communications, with a series of signal processing modules to improve data throughput and counter channel fading. Conventional hardware solutions, such as digital signal processors (DSPs) and more recently, graphic processing units (GPUs), provide various degrees of parallelism, yet they both fail to take into account the cyclical and consecutive character of WBP. Furthermore, the large amount of data in WBPs cannot be processed quickly in symmetric multiprocessors (SMPs) due to the unpredictability of memory latency. To address this issue, we propose a hierarchical dataflow-driven architecture to accelerate WBP. A pack-and-ship approach is presented under a non-uniform memory access (NUMA) architecture to allow the subordinate tiles to operate in a bundled access and execute manner. We also propose a multi-level dataflow model and the related scheduling scheme to manage and allocate the heterogeneous hardware resources. Experiment results demonstrate that our prototype achieves 2× and 2.3× speedup in terms of normalized throughput and single-tile clock cycles compared with GPU and DSP counterparts in several critical WBP benchmarks. Additionally, a link-level throughput of 288 Mbps can be achieved with a 45-core configuration.

Implementing LiDAR-based 3D object detection algorithms in practical autonomous driving situations presents a significant challenge. In current research algorithms, the inherent sparsity and randomness of point cloud data necessitate significant memory usage and frequent data read/write operations during preprocessing. Such demands are not well-suited for terminal devices with stringent real-time requirements and constrained resources. In this paper, we present a packetized processing Pillar Feature Net accelerator for LiDAR 3D object detection. By integrating voxelization and feature extraction into a pipelined architecture, the proposed accelerator significantly reduces the storage requirements for point cloud data and enhances the speed of feature extraction and pseudo-image generation. Experimental results indicate that the proposed method improves the computational throughput from point cloud data to pseudo-image generation by 1.2 times and eliminates the need for off-chip memory access during preprocessing.

Autonomous driving technologies are swiftly evolving, characterized by two main strategies: Single-Vehicle Autonomous Driving (SVAD) and Vehicle-Infrastructure Cooperative Autonomous Driving (VICAD). SVAD depends entirely on the vehicle’s internal sensors and processing capabilities, whereas VICAD benefits from a synergistic network combining roadside infrastructure, connected vehicles, and cloud services to boost safety and efficiency. Nevertheless, VICAD encounters challenges with high-bandwidth data transmission and perception latency. To mitigate these concerns, we introduce an innovative intelligent roadside unit (I-RSU) platform integrating perception, computing, and communication into one cohesive system. The platform features dual neural processing units (NPUs) for the effective extraction of images and LiDAR features, alongside a C-V2X communication module, all realized on a Field-Programmable Gate Array (FPGA). This setup minimizes latency and expenses by enabling computation near the sensors and facilitating selective data transmission. Our system also supports multi-modal fusion, enhancing overall perception and safety. Through extensive real-world trials and simulations, our system demonstrates a substantial reduction in end-to-end latency, providing a scalable solution for VICAD scenarios.

Cyber attacks on Cyber Physical Systems (CPSs), especially on those critical infrastructures poses severe threat on the public security. Among them, a special kind of attack, False Data Injection (FDI), can bypass the surveillance of state-estimation-based bad data detection mechanism silently. In this paper, we exploited the strong ability of Recurrent Neural Network (RNN) on time-series prediction to recognize the potential compromised measurements. It makes our proposed method practicable in real-world scenario that no labeled data is required during all stages of algorithm. An experiment on IEEE-14 bus test system is conducted and shows a promising result that our proposed method is able to detect FDI attack with high precision and high recall.