Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) has emerged as a compelling candidate for embedded memory due to its non-volatility, high endurance, and low power consumption. However, manufacturing process limitations result in low tunnel magnetoresistance ratios (TMR), leading to narrow read windows. Therefore, high-performance trimming is required, yet existing self-trimming schemes face challenges in balancing trimming time, accuracy, and flexibility. To address these issues, this paper proposes a Dynamic Stepsize Single-write Pattern Trimming (DSPT) algorithm that uses dynamic step sizes and a single-write pattern to rapidly lock the read window boundary range, followed by binary search for precise boundary determination, thereby reducing trimming time while maintaining high accuracy. A parallel variant, DSPT_P, is further proposed, allowing each sense amplifier (SA) to shift gears independently in advance and introducing an Address Reliability Limit (ARL) for result assessment. Finally, a BuiltIn Self-Test (BIST) architecture is proposed to implement the proposed trimming schemes.

The accurate extraction of interconnect parasitic capacitance is a critical issue for designing VLSI circuits. To improve the efficiency of parasitic capacitance extraction, we present in this paper an adaptive incremental learning (AIL) strategy to build the parasitic capacitance extraction pattern model. The proposed model is a deep neural network (DNN) trained using adaptive incremental learning, or AIL-DNN. The key ideas are as follows: Firstly, the parametric space is divided into several subspaces called regions. And then a small number of training samples and test data are collected by Latin hypercube sampling (LHS); Secondly, a DNN model is trained and tested. The regions with large prediction errors are determined based on the average relative errors of test, which are called the training ineffective regions; Then, according to the ineffective regions, the sampling density is adjusted, that is, a new training dataset is prepared by adaptive resampling; Finally, incremental learning (IL) is used to make the DNN train new samples and update the network. The procedure of adaptive resampling, training and testing iterates until the test error reaches the predefined prediction accuracy. The proposed AIL-DNN can improve the efficiency and accuracy of DNN training with a reduced number of samples, and the trained DNN model can be used for the rapid extraction of parasitic capacitance. In this work, the prediction results of AIL-DNN and of the traditional DNN for two given interconnect patterns are compared. The results show that the size of training dataset required by AIL-DNN is about 20% of that of the traditional DNN with the similar accuracy. This significantly reduces the computational cost and time of dataset preparation.

A PIN power diode model based on moving mesh method for circuit simulation is presented. For high voltage large capacity fast recovery diode with a long length of n-base, the depletion region edge at both side of the quasi-neutral region, where carrier concentration change steeply, are moving constantly during turn-off. To achieve a tradeoff between execution speed and acceptable accuracy, a moving mesh method based on equidistribution principle is applied considering the characteristic of carrier profile distribution of high voltage FRD. With high simulation speed, the power diode model is shown to give agreement with the experiment waveforms.