Modern Field-Programmable Gate Arrays (FPGAs) are widely utilized across various fields, including artificial intelligence accelerators and Internet of Things (IoT) devices, due to their flexibility and low-cost development potential. However, the problem of “recycled FPGAs” being fraudulently sold as new has grown increasingly severe. This raises significant concerns about reliability degradation caused by performance deterioration, especially in critical applications such as medical and communication systems. Many studies have proposed methods for detecting recycled FPGAs based on delay degradation analysis using Ring Oscillators (ROs). However, the state-of-the-art approach requires a comprehensive evaluation of paths within all lookup tables, leading to increased testing costs and database management overhead. To address this issue, a method combining exhaustive fingerprinting (X-FP) methodology with an advanced RO design is proposed, where a statistical Virtual Probe (VP) model is used to predict the delay of the RO. This research aims to achieve high-accuracy predictions with fewer data points by employing Gaussian Process Regression (GPR) instead of the VP model. This demonstrates that, with actual silicon data, the proposed custom (GPR) improves prediction accuracy by 20% compared with state-of-the-art VP model methods with 50% less training data. The two proposed models demonstrated better performance than Naive GPR, achieving 9% and 7% higher prediction accuracy, respectively. The predictions were further verified using an optimized Autoencoder. The model successfully detected both 10-days and 14-days aged FPGAs among the new ones, achieving 100% overall accuracy using only 10% and 3% training data, respectively. While although the training data predicted by the VP can also detect aged FPGAs, it cannot properly classify all aged and non-aged FPGAs in both 3% and 10% training scenarios. Finally, for further verification in the case of both new and aged FPGA, after prediction, the logistic regression classifier was trained with both old and new FPGA data, achieving 100% correct classification.

Wafer-level performance prediction has been attracting attention to reduce measurement costs without compromising test quality in production tests. Although several efficient methods have been proposed, the site-to-site variation, which is often observed in multi-site testing for radio frequency circuits, has not yet been sufficiently addressed. In this paper, we propose a wafer-level performance prediction method for multi-site testing that can consider the site-to-site variation. The proposed method is based on the Gaussian process, which is widely used for wafer-level spatial correlation modeling, improving the prediction accuracy by extending hierarchical modeling to exploit the test site information provided by test engineers. In addition, we propose an active test-site sampling method to maximize measurement cost reduction. Through experiments using industrial production test data, we demonstrate that the proposed method can reduce the estimation error to 1/19 of that obtained using a conventional method. Moreover, we demonstrate that the proposed sampling method can reduce the number of the measurements by 97% while achieving sufficient estimation accuracy.