The Posit number system provides a promising alternative to traditional floating-point (FP) formats for deep neural network (DNN) training by offering tapered precision and a wide dynamic range, addressing key limitations of conventional FP formats. While recent research has demonstrated the advantages of Posit-enabled training and inference for fixed-precision applications, the development of mixed-precision frameworks has been hindered by the absence of rounding algorithms for transitioning between Posit formats. This dependency has limited the practical adoption of Posits in DNN workflows. In this article, we present a Posit-based Mixed Precision Training and Inference (PMP) framework, leveraging Posit32, Posit16, and Posit8 for distinct computational stages. Posit32 ensures numerical stability in critical operations, Posit16 balances precision and efficiency for intermediate computations, and Posit8 significantly reduces memory usage during inference. Specifically, we introduce algorithms for converting Posit32 representations into Posit16 and Posit8 , and vice versa, under two rounding modes: deterministic and stochastic. Stochastic rounding is employed to mitigate precision loss in low-precision arithmetic. Furthermore, we propose a hardware-efficient Posit Multiply-Accumulate (pMAC) Unit that integrates deterministic and stochastic rounding modules, enabling efficient mixed-precision computations. We validate our framework on ResNet-18, ResNet-50, ResNet-152, MobileNet-v2, VGG-16, and EfficientNet-B7 (trained on ImageNet), YOLOv2 (trained on PASCAL VOC 2012), and BERT (trained on WikiText-2). Experimental results demonstrate up to 1.5× training speedup with Posit16 -based PMP framework and up to 6.5× training speedup with Posit8 -based PMP framework when compared with fixed-precision FP32 training, while maintaining comparable or superior accuracy. Moreover, hardware results show that the design overhead of integrating proposed deterministic and stochastic rounding modules with the pMAC unit is estimated to be around 4.6% only.

Modern technology is relying on hardware accelerators to achieve enhanced performance of computing systems. In the modern computing paradigm, floating point representation of numbers has gained popularity owing to its wide dynamic range. Rounding of floating point numbers to integer is used in modern processor architectures e.g., ARM and Intel's architecture (IA) as well as in specific applications such as multimedia. However, the academic literature lacks discussion on hardware designs for rounding binary floating point numbers to integer in different rounding modes. This article presents novel efficient algorithms and hardware architecture designs for rounding binary floating point numbers to the integer for the following rounding modes: round towards zero, round up (towards positive infinity), round down (towards negative infinity), round to the nearest integer, and round to nearest even. The article also proposes an integrated multi-mode rounding (IMR) algorithm and hardware design which can be configured to a specific rounding mode among the above-mentioned five modes. This article proposes a mantissa bit of rounding (MBR) to determine the condition of rounding for the various modes. The MBR is identified on the basis of the dynamic range and precision features of floating point representation. To the best of our knowledge, we present the individual as well as an integrated hardware design for the various rounding modes for the first time in the literature. The proposed designs have been implemented on an FPGA platform to analyze the design metrics such as area, delay, and power. The results imply that the proposed designs are suitable to aid the intended hardware accelerators as they are efficient in terms of the design parameters. Moreover, this article presents the integration of the proposed rounding hardware design with the compression processor and evaluates the integration overhead which is found to be nominal (<1%).

Reusable third-party intellectual property (3PIP) cores within the supply chain are vulnerable to hardware threats such as IP piracy and false claim of ownership. Securing the reusable IP cores is vital to protect the original vendor from a substantial revenue loss and his/her brand value. This paper presents a novel hardware IP core watermarking methodology based on voice biometric signature to enable detective control against IP piracy and resolve IP ownership claim. To the best of our knowledge, this is the first voice biometric-based hardware IP protection technique. This paper proposes a novel methodology for generating a unique voice signature template using distinct voice features, viz. jitter and shimmer, along with pitch and intensity values at different timestamps. We present a high-level synthesis (HLS) design methodology of embedding a voice signature digital template during the register allocation phase to generate secured IP cores. Results and analysis imply that the proposed approach can significantly improve security in terms of stronger authorship proof and higher tamper tolerance compared to the existing IP watermarking approaches. Additionally, we also analyze the uniqueness of a voice signature and its security against forgery attack. We achieve higher security at negligible design cost overhead.

This paper presents a novel hardware security technique that leverages handwritten signature image features for securing intellectual property (IP) cores, such as digital signal processing (DSP) cores, against IP piracy and false claim of IP ownership threats. In our approach, an IP vendor's handwritten signature image features are first converted into a corresponding digital template, followed by mapping into hardware security constraints and implanting them into the design during high level synthesis (HLS) process. This paper presents methodologies of extracting feature set of a handwritten signature through sampling and of encoding of the samples into binary values using a tree based encoding, for generating the digital template. The results of the proposed approach are assessed in terms of strength of IP ownership proof, security against a forged signature and impact of embedding signature constraints on design cost. The results revealed that the proposed approach provides robust security at negligible design cost overhead and also outperforms state of the art hardware security approaches for DSP cores.

This article presents a novel facial biometrics-based hardware security methodology to secure hardware accelerators [such as digital signal processing (DSP) and multimedia intellectual property (IP) cores] against ownership threats/IP piracy. In this approach, an IP vendor's facial biometrics is first converted into a corresponding facial signature representing digital template, followed by embedding facial signature's digital template into the design in the form of secret biometric constraints, thereby generating a secured hardware accelerator design. The results report the following qualitative and quantitative analysis of the proposed biometric fingerprint approach: 1) impact of five different facial biometrics constraints on probability of coincidence (Pc) metric (indicating strength of digital evidence). The proposed approach achieves a very low Pc value in the range of 1.54E-5 to 2.01E-5; 2) impact of different facial feature set of a facial biometric image on total number of generated secret constraints and Pc. As evident, for all facial feature sets implemented, Pc ranges between 3.31E-4 and 2.01E-5; and 3) comparative analysis of proposed approach with recent work, for different DSP applications and five different facial biometric images, in terms of Pc. As evident, the proposed approach achieves significantly lower Pc, compared with recent work.

This article presents a novel methodology to secure hardware accelerators (such as digital signal processing (DSP) and multimedia intellectual property (IP) cores) against ownership threats/IP piracy using biometric fingerprinting. In this approach, an IP vendor's biometric fingerprint is first converted into a corresponding digital template, followed by embedding fingerprint's digital template into the design in the form of secret biometric constraints; thereby generating a secured hardware accelerator design. The results report the following qualitative and quantitative analysis of the proposed biometric fingerprint approach: 1) impact of 11 different fingerprints on probability of coincidence (Pc) metric. As evident, the proposed approach achieves a very low Pc value in the range of 2.22E-3 to 4.35E-6. Further, the biometric fingerprint achieves total constraints size between minimum 350 bits to maximum 895 bits; 2) impact of six different resource constraints on the design cost overhead of JPEG compression hardware postembedding biometric fingerprint. As evident, for all the resource constraints implemented, the design cost overhead is 0%; and 3) comparative analysis of proposed biometric fingerprint with recent work, for five different signature strength values, in terms of Pc. As evident, the proposed approach achieves minimum 3.9E+2 times and maximum 6.9E+4 times lower Pc, when compared to recent work.