Ring Oscillator Physical Unclonable Functions (RO-PUFs) exploit the inherent manufacturing process variations, such as systematic and stochastic variations, to generate secret PUF responses that are unique to the device. Stochastic variations are random, while systematic variation exhibits a strong spatial correlation. Therefore, systematic process variation reduces the randomness of the PUF response. This lowers the ability of a PUF response to uniquely identify and authenticate individual devices. Further, the impact of systematic variation is paramount when the two ROs in comparison are placed far apart. Comparing the ROs that are close to each other does improve the randomness, but the responses generated are unreliable and limiting the possible Challenge-Response Pairs (CRPs). In this article, we are proposing a method to reduce the impact of systematic process variation on the RO oscillation frequencies by using Principal Component Analysis (PCA). Principal Components (PCs) model the directions of systematic and stochastic variation present on a device. By projecting the oscillation frequencies in the direction of stochastic variation, the impact of systematic variation can be reduced. Our proposed method neither restricts the placement of ROs to close groups nor limits the possible CRPs. The method is evaluated on a large population of 218 Xilinx Artix-7 FPGAs. To evaluate the efficiency of the proposed method, we purposely paired the ROs that are placed far apart on the FPGA fabric. Results obtained prove the ability of the proposed method in removing the impact of systematic variation on the oscillation frequencies and thereby producing truly random responses.

Modern analog placement techniques require consideration of current path and symmetry constraints. The symmetry pairs can be efficiently packed using the symmetry island configurations, but not all these configurations result in minimum gate interconnection, which can impact the overall circuit routing and performance. This article proposes the first work that reformulates this problem considering all of them together in the form of parallel current path (PCP) constraints. PCP constraints, in addition to monotonic current paths, also consider partial-monotonic current paths to generate a more compact placement. We use a novel two-step approach to detect symmetry-feasible sequence-pairs (SFSPs) without doing placement construction by using representative sequence-pair (RSP). Then a placement algorithm satisfying these constraints is formulated to reduce a vast search space via efficient sequence pair manipulation. The experimental results show that this formulation and algorithm can generate multiple placement solutions that satisfy all the constraints in a more tightly packed configuration, resulting in smaller wirelength, reduced parasitics, and thus better post-layout performance.

Modern analog placement techniques require consideration of current path and symmetry constraints. The symmetry pairs can be efficiently packed using the symmetry island configurations, but not all these configurations result in minimum gate interconnection, which can impact the overall circuit routing and performance. This paper proposes the first work that reformulates this problem considering all of them together in the form of Parallel Current Path (PCP) constraints. Then a placement algorithm satisfying these constraints is formulated to reduce a vast search space via efficient sequence pair manipulation. Experimental results show that this formulation and algorithm can satisfy all the constraints in a more tightly packed configuration, resulting in lesser routing length, reduced parasitics and thus better post-layout performance.