This work presents a 0.4-V supply, 12-nW reverse bandgap voltage reference (BGR) with single BJT and indirect curvature compensation. To achieve sub-0.5V operation, the proposed BGR employs the reverse BGR based complementary-to-absolute-temperature (CTAT) voltage generator, which does not suffer from the settling error and thus reducing the biasing current for the BJT. The reduction in BJT biasing current can reduce the power consumption, thus relieving the burden on the$2\times $charge pump as well, in which the minimum supply voltage of the proposed BGR decreases down to 0.4 V. In this paper, we employ a differential pair proportional-to-absolute-temperature (PTAT) voltage generator to provide a sufficiently large PTAT voltage. To suppress the temperature coefficient (TC) under limited power and voltage budgets, we propose using a nA level PTAT plus nonlinear current to bias both the BJT and PTAT voltage generator. This approach provides an indirect voltage curvature compensation. The proposed reverse BGR fabricated in 65 nm CMOS, occupies an active area of 0.0470 mm2. Measurement results from 8 chips show an average reference voltage of 487.4 mV under 0.4 V supply, with an average TC of 28.4 ppm/°C over a temperature range from -40°C to 100°C, while consuming only 12 nW power.

This paper presents a segmented curvature-compensated bandgap voltage reference (BGR) with low temperature coefficient (TC) and power consumption across a wide temperature range. In this work, we achieve temperature segmentation by comparing voltage instead of current, as in the conventional method, significantly reducing power consumption. Furthermore, we examine the trade-off between TC and power consumption, focusing on optimizing the number of temperature segments. In the core circuit, we utilize a regulated cascode current mirror to minimize channel length modulation induced error existing in the current-based BGR topology. We also introduce a replica structure to prevent oscillation and design comparators with the hysteresis characteristic to address noise influence. The proposed BGR, implemented in 65 nm CMOS, occupies an active area of 0.058 mm2. Measurement results of 6 chips show that the achieved reference voltage of 431.3 mV under 1 V supply has the best TC of 8.7 ppm/°C over a temperature range of −40 °C to 90 °C, consuming 740 nW at 20 °C.

This paper presents a switched-capacitor network (SCN) based bandgap voltage reference (BGR) for IoT applications. The proposed BGR employs a dual proportional-to-absolute-temperature (PTAT) clock topology to achieve both high precision and low power over a wide temperature range while relaxing the capacitor size requirements. Specifically, the fast PTAT clock assists in reducing the output voltage ripple of the dual-branch interleaved$2\times $charge pump (CP). Meanwhile, the slow PTAT clock controls the voltage divider SCN to relax the settling error at low temperature and the leakage-induced error at high temperature simultaneously, resulting in lower power consumption and smaller temperature coefficient (TC). We also propose a replica$V_{\mathrm {EB}}$generation branch in the series-parallel SCN to improve the BGR output TC due to the finite settling time during switching. Fabricated in 65nm standard CMOS, measurement results show that the proposed BGR obtains a TC of 32 ppm/°C at 0.5V supply within −40 °C to 120 °C. The line regulation is 3.3mV/V or 0.66%/V from 0.5V to 1V. Based on 10-chip measurement results, we obtain a$3\sigma / \mu $variation of 1.37% before trimming, while 0.25% after applying one-point trimming at 20°C.

This paper presents the DC analysis of the Negative Output Elementary Luo Converter (NOELC), which includes the continuous-conduction mode (CCM) voltage gain and the boundary condition between the CCM and the discontinuous-conduction mode (DCM). The main features of the NOELC are the high gain with small ripple and the reverse output. Additionally, we address the parameters design of the NOELC and propose an output voltage ripple estimation method. Through MATLAB Simulink simulation, we further demonstrate that the parameters design and the output voltage estimation method can achieve more accurate results when compared with those from the conventional one.