Symmetrical six-phase motors offer superior fault-tolerant ability, particularly with neutral point connection (CNP) configuration. In the structure of CNP, non-negligible zero-sequence current (ZSC) is generated since zero-sequence loop has been formed between the dual inverters. This paper proposes a novel zero-sequence current elimination (ZSCE) pulsewidth modulation (PWM) scheme for S6-PMSM with CNP. The switching state combinations of dual inverter is mapped to three orthogonal sub-planes using decoupling coordinate transformation, and combinations of vectors with zero zero-sequence voltage (ZSV) are picked to generate the same common mode voltage (CMV) of two inverters in the synthesis process of reference vector. The two CMVs can cancel out each other to remove the modulated ZSV source and eliminate the ZSC. The superiority of the proposed ZSCE PWM method is demonstrated by the experiment.

The single-stage multiport inverter (SSMPI)-fed motor drives enable direct connection from the dc-side energy sources to the ac motor without utilizing any dc/dc converters, which feature high power density and high efficiency of the overall system. However, the output power of each source is highly coupled with the motor control in this topology, which provides poor flexibility of power control. To address this problem, a decoupling control strategy is proposed in this paper. First, an asymmetrical carrier-based modulation strategy is adopted to ensure the high performance of the motor control by fully considering the voltage variation of sources. Then, injecting different values of the zero-sequence voltage adds a degree of freedom for controlling the output power of sources. With the proposed method, the flexible power control is realized without affecting the performance of the motor control. Finally, the effectiveness of the proposed control scheme is verified through experiments on a permanent magnet synchronous motor (PMSM)-based laboratory prototype.

This paper proposes a dead time compensation method based on current ripple prediction (CRP) for three-level inverters. First, the dead time effect in three-level inverters is analyzed, including the influence of dead time freewheeling and switching process caused by parasitic capacitors, and the time delay variation curves of the phase voltage switching edges with the phase current are obtained. Then, the actual phase current is reconstructed using the CRP method and the sampled low-frequency current. Thus, the compensation time of the switching edges can be accurately calculated. Simulation and experimental results are provided to validate the effectiveness of the proposed method in both reducing phase current distortion and improving the common-mode voltage elimination effect.

The Internal-Parallel Multilevel Converter (IPMC) with reduced device count is implemented to drive the dual three-phase permanent magnet synchronous motor (DTP-PMSM) forming multilevel multiphase motor drives. However, due to the restriction of the low switching frequency (LSF) module sharing, only the parallel high switching frequency (HSF) switching states can keep interleaving operation, whereas the proportional-integral (PI) control, the resulting voltage reference, and the LSF switching state remain simultaneous, which leads to asymmetric pulse width modulation (PWM) waveform and significant harmonics. In this paper, the effect of asymmetric PWM waveform on current and torque harmonics is investigated. Meanwhile, a decoupled modulation strategy with optimized interleaved PWM is proposed to solve the problem, thus achieving the reduction of the corresponding order and switching frequency torque harmonics with a certain improvement in the current ripple. The experimental results with the IPMC-fed DTP-PMSM drive prototype are provided to verify the validity and superiority of the proposed modulation strategy compared to the traditional interleaving scheme and the non-interleaving technique.

The dc-link current is an important indicator for the design and selection of dc-link capacitors for voltage source inverter (VSI). The traditional dc-link current analysis for two-level three-phase VSI based motor drive only considers ac fundamental phase current and neglect the ac high-frequency current ripple caused by the pulse width modulation (PWM) process. Thus, this paper introduces an accurate analytical method of the dc-link capacitor current by taking the real-time ac high-frequency current ripple into consideration. Moreover, the accurate calculation of rms current on the dc-link capacitor has been provided with the traditional PWM methods, and the time-domain comparison of dc-link current has been studied under the wide range of adjusting speed and power factor. Simulation and experimental results are both provided to validate the accuracy of the proposed method.

In low-voltage energy storage microgird systems, the quasi-single-stage architecture is a promising alternative to improve the efficiency, which contains a direct power flow path from the battery to the inverter, resulting in reduced power losses by dc/dc converter. However, the unbalanced dc-link voltage of two ports certainly generates asymmetric space vectors. Thus, how to design the modulation strategy under this scenario is the major challenge. Meanwhile, the power losses are not only determined by the topology, but the device material such as gallium nitride (GaN) also has a significant impact on it. Therefore, a novel hybrid Si/GaN-based quasi-single-stage converter (HSG-QSSC) is proposed in this paper. Furthermore, a simplified space-vector modulation (SVM) scheme is presented to concentrate all the high-frequency switching events on the GaN HEMTs while the Si IGBTs operate with low frequency and avoid complicated triangle functions. As a result, the total power losses are reduced due to the decoupled frequency switching, and the high efficiency of calculation is achieved. Islanded microgrid experimental results with a hybrid Si/GaN active-neutral-point converter (ANPC) prototype are provided to verify the feasibility and effectiveness of the presented modulation scheme.

The open winding permanent magnet synchronous machine (OW-PMSM) driven by dual two-level three–phase inverters with common dc bus have become common in variable speed applications due to the inherent advantages. This paper makes analysis of the characteristic of different modulation schemes for three-phase OW-PMSM, including the dc-link capacitor current which determines the lifetime of dc-link capacitor, and the conduction losses of the dual inverters which influence the temperature rise and thermal stress of each inverter. With the theoretical analysis and comparison, the proposed phase-shift sinusoidal pulse width modulation (PS-SPWM) is proved to have better performance than the conventional signal rotation space vector pulse width modulation (SVPWM) in some respect. Simulation and experimental results are both provided to validate the effect of the characteristic for the modulation schemes.

This paper introduces a paralleled three-phase four-leg inverters and the corresponding pulse width modulation (PWM) method for the purpose of reduction the common mode current (CMC) and common mode electromagnetic interference (EMI). Considering the control principle of three-phase four-leg to limit the common mode voltage and the characteristic of paralleled inverters, the simple PWM scheme for paralleled three-phase four-leg inverters can be deduced. In the modified topology, the low frequency and high frequency models can be set up to determine the load parameters of the extra phase. The results based on MATLAB SIMULINK and experiments are provided to validate the proposed method.