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Ya-Chieh Lai

dblp:233/8107 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
design for manufacturability
0.412019
DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder · DAC 2019
Electronic design automation › design for manufacturability
layout pattern generation
0.412019
DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder · DAC 2019
Electronic design automation
physical design
0.412019
DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder · DAC 2019

Methods — techniques the papers use, named apart from their topics

generative machine learning · 0.4convolutional autoencoder · 0.4
YearPublicationVenuePosition
2019 Detecting multi-layer layout hotspots with adaptive squish patterns
abstract
Layout hotpot detection is one of the critical steps in modern integrated circuit design flow. It aims to find potential weak points in layouts before feeding them into manufacturing stage. Rapid development of machine learning has made it a preferable alternative of traditional hotspot detection solutions. Recent researches range from layout feature extraction and learning model design. However, only single layer layout hotspots are considered in state-of-the-art hotspot detectors and certain defects such as metal-to-via failures are not naturally supported. In this paper, we propose an adaptive squish representation for multilayer layouts, which is storage efficient, lossless and compatible with deep neural networks. We conduct experiments on 14nm industrial designs with a metal layer and its two adjacent via layers that contain metal-to-via hotspots. Results show that the adaptive squish representation can achieve satisfactory hotspot detection accuracy by incorporating a medium-sized convolutional neural networks.
Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu 0001
ASP-DAC4
2019 DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder
abstract
VLSI layout patterns provide critic resources in various design for manufacturability researches, from early technology node development to back-end design and sign-off flows. However, a diverse layout pattern library is not always available due to long logic-to-chip design cycle, which slows down the technology node development procedure. To address this issue, in this paper, we explore the capability of generative machine learning models to synthesize layout patterns. A transforming convolutional auto-encoder is developed to learn vector-based instantiations of squish pattern topologies. We show our framework can capture simple design rules and contributes to enlarging the existing squish topology space under certain transformations. Geometry information of each squish topology is obtained from an associated linear system derived from design rule constraints. Experiments on 7nm EUV designs show that our framework can more effectively generate diverse pattern libraries with DRC-clean patterns compared to a state-of-the-art industrial layout pattern generator.
Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu 0001
DAC4