An on-chip high-frequency sinusoidal signal generator with a calibration circuit based on a coarse-fine delay cell is presented in this work. The proposed signal generator is based on harmonic cancellation by adding scaled and time-shifted versions of a periodic signal. However, as we increase the target frequency of the generated signal, harmonic cancellation can be severely degraded by timing issues, degrading in turn the spectral purity of the generated signal. This paper proposes an architecture of a harmonic cancellation-based sinusoidal signal generator including a calibration circuit. The calibration circuit is based on a coarse-fine delay cell that can correct timing inaccuracies. Postlayout simulations of the proposed generator in FD-SOI 28 nm technology show a THD better than −60 dB in the frequency range from 173 MHz to 2 GHz.

Harmonic cancellation techniques have been exploited for the on-chip generation of high-linearity sinusoidal test stimuli. The sinusoidal signal is generated by combining time-shifted and scaled versions of a periodical signal, in such a way that by properly choosing the time-shifts and weights, the lower order harmonics are canceled. However, process variations and mismatch can degrade the effectiveness of the harmonic cancellation, since precise time-shifts and scale ratios are required. In this regard, timing inaccuracies are especially harmful in the implementation of high-speed harmonic cancelling generators. In this paper, we propose an on-chip calibration architecture that can correct the phase-shift and duty-cycle of the signals with the help of a negative feedback loop. Electrical simulation results at transistor level show the feasibility of the calibration technique for a sinusoidal signal generator implemented in ST 28 nm FD-SOI technology. Obtained results show a Total Harmonic Distortion (THD) better than -60 dB after calibration in an output frequency range from 200 MHz to 4 GHz.

On-chip sinusoidal signal generators are a key element for enabling a wide variety of DfT and BIST applications for AMS-RF integrated circuits. Harmonic cancellation techniques have been recently proposed for the efficient implementation of high-quality embedded sinusoidal signal generators. However, harmonic cancellation techniques, based on phase-shifting and combining a set of periodic signals, rely on precise and accurate phase-shift control which makes them very sensitive to timing issues due to mismatch, noise, etc. Timing issues can severely limit the performance of these generators especially in high-frequency applications where precise timing becomes challenging. In this paper, we analyze the effects of timing inaccuracies on high-speed harmonic cancellation generators and we propose circuit techniques for mitigating them. Electrical simulation results on a 1.45 GHz sinusoidal signal generator implemented in ST 28 nm FDSOI technology are provided to validate our proposals.