The technology scaling has boosted the importance and gravity of radiation faults. Hardening techniques are required to ensure a high level of reliability, mainly to the harsh critical applications. Hardware redundancy remains the most adopted option to deal with fault tolerance, mostly the TMR technique. However, the weakness of this technique is the voter circuit. This paper investigates the robustness of nineteen majority voter designs in the presence of a SET. The analysis explores critical diffusion areas and LET threshold. The results show designs with 3X difference in the number of critical diffusion areas and 6X in the LET threshold.

The aggressive technology scaling has significantly affected the circuit reliability. Several techniques have been explored to mitigate the scaling effects and guarantee a satisfactory reliability level. In this context, estimating circuit reliability is crucial and a challenge that has not yet been overcome. For decades, traditional reliability estimation techniques have used fixed logic gates reliability values. Recently, methods demonstrate that using fixed gate reliability values compromises the accuracy of the analysis. This work evaluates the impact of the estimated logic gate susceptibility in the reliability of several benchmarks circuits mapped with different sets of logic gates. The obtained results show a discrepancy in the reliability of the same circuit. However, the change in the reliability behavior may be considered the main contribution of this work. The utilization of fixed reliability values for logic gates provides reliability values inversely proportional to the number of gates in the circuit. The used approach captures the logical characteristics of the gates. The same circuit mapped with basic gates presents a difference in MTBF of 20%, while the one mapped with a complex set of gates is bigger than 70%.

Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthesis rely on SAT and Boolean methods to exactly implement the care set, we investigate learning in logic synthesis, attempting to trade exactness for generalization. This work is directly related to machine learning where the care set is the training set and the implementation is expected to generalize on a validation set. We present learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020. The goal of the competition was to implement 100 functions given by a set of care minterms for training, while testing the implementation using a set of validation minterms sampled from the same function. We make this benchmark suite available and offer a detailed comparative analysis of the different approaches to learning.