Analog to Digital Converters based on Voltage Controlled Oscillators are assumed very tolerant to sampling clock inaccuracies. This is due to the first-order shaping of sampling-induced errors, which appear indistinguishable from VCO phase quantization errors. A closer look to VCO-ADCs reveals that jitter errors can be problematic under different kinds of inputs and are affected by circuit impairments. This paper theoretically analyzes the behavior of pseudo differential VCO-ADCs in the presence of clock jitter and provides simulations of practical cases. In spite of being noise-shaped, the error induced by jitter is shown to depend on the input signal power. Afterwards, we analyze how VCO gain mismatch and offset among oscillators can affect clock jitter robustness. Also, in-band noise degradation due to out-of-band signal interferers is described.

One of the limitations of conventional VCO-ADCs is the restriction to first-order noise shaping. True VCO-ADC architectures have been proposed to increase the noise-shaping order by cascading several VCO integrators, but without requiring analog feedback loops. A high noise-shaping order allows to reduce the input VCO frequency compared to a conventional VCO-ADC with similar dynamic range, which improves power consumption. Prior-art True VCO-ADC architectures represent state variables either with a unity-weighted code or with a single-bit. Unity-weighted encoding is a natural choice when ring oscillators are selected as loop filter integrators. However, chip area restrictions force unity-weighted state variables to have few levels. A reduced number of levels in the state variables limits the dynamic range of True VCO-ADCs. In this paper, we experimentally demonstrate a second-order audio VCO-based ADC that uses ring oscillators as integrators but employs Gray and binary encoded state variables. As a consequence, the complexity and area of the True VCO-ADC architecture is reduced, breaking the barrier that limits the dynamic range of prior designs. The proof-of-concept chip shows a dynamic range of 103 dB achieving a peak SNDR of 76.5 dB-A with a power of 250$\mu$W occupying 0.095$\text{mm}^2$in 130 nm CMOS.

This paper introduces a new CMOS implementation of a spiking Leaky Integrate-and-Fire (LIF) neuron. The circuit does not require any analog circuit block such as comparators or current sources thanks to the use of a ring-oscillator as an integrator and a phase delay detector as threshold logic. The circuit admits both excitatory and inhibitory input spiking signals whose pulse width does not affect the computation. Instead of powering the ring oscillators from a power supply, the input spikes charge a capacitor bank which powers the ring oscillator. The paper describes the operation of the neuron analytically for the input integration and the membrane voltage decay. Also, a circuit-level simulation in 65nm CMOS technology has been performed, achieving a power efficiency of < 40fJ/spike.

A ring-oscillator based circuit is proposed for features extraction tasks within smart speech recognition and voice activity detectors applications. The architecture performs all the operations needed for conventional features extraction but making use of only time-encoded based circuits in the analog domain. This results in a compact and simple structure, easily scalable and suitable for the deepest CMOS nodes leading for ultra-low and small solutions. The proposal is described theoretically and functionally checked with behavioral simulations in MATLAB. Additionally, the filtering stage is designed in a 65-nm process and validated with transient simulations providing promising results referring estimated power and area.

This work introduces a new VCO-ADC architecture. The power supply nodes of the inverters in a ring oscillator are sorted in two sets, and connected to two different input signals. We show in this paper that the oscillator frequency of such configuration reacts to the product of the two inputs. Therefore, the ring oscillator can be used both as a mixer and to digitally acquire the lowpass converted component. A first system-level approach is made to optimize the distortion by a proper number of taps in the ring oscillator. To confirm the system level predictions, some circuit simulations have been made. As a result, it is observed that VCO non-linearity limits the SNDR in a similar way as in conventional low pass VCOADCs. In a 65nm CMOS process, 55 dB of SNDR is achieved in a 5-MHz bandwidth for a 1 MHz downconverted signal, using a sampling clock of 2.5 GHz and input signals centered in 70 MHz and 71 MHz.

The main limitation of voltage-controlled oscillator based analog-to-digital converters (VCO-ADC) is the VCO non-linear voltage-to-frequency response, especially with ring-oscillators. This issue strongly restricts the final resolution we are able to get from the converter. In addition, flicker noise is a limitation for low-bandwidth applications. We propose a novel way of compensating both the VCO non-linearity and the phase noise effects. By means of a time varying switched-capacitor circuit, we build a purely analog compensation loop where jitter clock and DAC non-linearity do not suppose a limitation. The loop is closed with an opamp that provides gain to the compensation operation. The idea is proposed theoretically and tested by simulations, showing a good performance for audio or sensing applications.