Although wake-up power-supply noise (PSN) leaves a more profound mark on IC performance than run-time PSN, it has received little attention in contemporary studies. This article addresses this gap by presenting a comprehensive mathematical model of wake-up PSN and introducing a novel strategy to temporally spread its impact via frequency modulation during the IC's sleep-to-active transition. Bringing this concept to reality, a framework of Sweeping Variable-Frequency Clock (SVFC) synthesis was realized in SCL 180 nm CMOS. Rigorous postlayout simulations on Cadence Virtuoso at a supply of 1.8 Volt reveal its finesse-achieving sub-10ps jitter and nearly 50% consistent pulse width across all frequencies and all process corners. Finally, benchmark analyses under DIP-40 package model substantiate the effectiveness of the approach with an average 63.6% improvement in wake-up PSN and 65.7% current and power savings across circuits under test, demonstrating a pathway to mitigate wake-up PSN and enhance IC reliability.

This research presents a novel approach for implementing an artificial neural network using an analog hardware architecture. The core components of this architecture consist of current-mode circuits, which represent the class, and a voltage-mode comparator. All current-mode circuits are designed to operate with minimal bias current. For the voltage comparator, which handles the final decision-making process, a low-voltage amplifier is utilized. The operational principles of the architecture are thoroughly detailed and applied in a power-efficient configuration, operating at sub-microWatt levels with low power supply rails (0.6 V). The proposed design is validated on real-world biomedical classification tasks, achieving impressive classification accuracy exceeding 93%. The implementation is realized using a 90nm CMOS process and developed within the Cadence IC Suite for both schematic and layout design. To ensure the robustness of the proposed classifier, Monte Carlo analysis, covering both process variations and mismatches, as well as corner analysis, are conducted. A comparative analysis of the post-layout simulation results with an equivalent software-based classifier and relevant literature confirms the effective performance of the proposed architecture.

In this article, a framework for the analog implementation of a deep convolutional neural network (CNN) is introduced and used to derive a new circuit architecture which is composed of an improved analog multiplier and circuit blocks implementing the ReLU activation function and the argmax operator. The operating principles of the individual blocks, as well as those of the complete architecture, are analyzed and used to realize a low-power analog classifier, consuming less than$1.8~\mu \text {W}$. The proper operation of the classifier is verified via a comparison with a software equivalent implementation and its performance is evaluated against existing circuit architectures. The proposed architecture is implemented in a TSMC 90-nm CMOS process and simulated using Cadence IC Suite for both schematic and layout design. Corner and Monte Carlo mismatch simulations of the schematic and the physical circuit (postlayout) were conducted to evaluate the effect of transistor mismatches and process voltage temperature (PVT) variations and to showcase a proposed systematic method for offsetting their effect.

This study introduces a design methodology pertaining to analog hardware architecture for the implementation of the learning vector quantization (LVQ) algorithm. It consists of three main approaches that are separated based on the distance calculation circuit (DCC) and, more specifically; Euclidean distance, Sigmoid function, and Squarer circuits. The main building blocks of each approach are the DCC and the current comparator (CC). The operational principles of the architecture are extensively elucidated and put into practice through a power-efficient configuration (operating less than 650 nW) within a low-voltage setup (0.6 V). Each specific implementation is tested on a brain tumor classification task achieving more than 96.00% classification accuracy. The designs are realized using a 90-nm CMOS process and developed utilizing the Cadence IC Suite for both schematic and physical design. Through a comparative analysis of postlayout simulation outcomes with an equivalent software-based classifier and related works, the accuracy of the applied modeling and design methodologies is validated.

Electrical Impedance Tomography (EIT) is a developing medical imaging technique which derives the conductivity distribution of a subject with significant temporal resolution. Despite the recent advances in both EIT reconstruction algorithms and hardware, the limited spatial resolution, i.e. low distinguishability between the inclusions, and the presence of artifacts remain the main issues. To address them, block sparse Bayesian learning (BSBL) frameworks have been adopted in EIT, based on the assumption of block-structured inclusions and using minimization of a Bayesian-form cost function in an unsupervised learning manner. To further improve the imaging quality and to enhance convergence speed we combine a Bound-Optimization (BO) and a weighted BSBL approach, introducing priorily estimated weights obtained by a single-step approach, to each block's hyperparameter estimation. Simulations based on 2D circular domains and evaluation using experimental and in-vivo data verify the proposed method's performance compared to traditional regularization and BSBL approaches.