Quantum computing (QC) is an emerging paradigm with the potential to transform numerous application domains by addressing classically intractable problems. However, its growing presence in cyberspace has introduced new security and privacy challenges. Similar to classical computing systems, the QC stack including software and hardware relies extensively on third parties, many of which are emerging and trust-seeking or less-trusted. This stack often contains sensitive intellectual property (IP) that demands protection. Unique features of quantum systems can enable classical-style attacks: for instance, crosstalk in multitenant settings can facilitate fault-injection attacks, while malicious calibration services can misreport error rates or miscalibrate qubits to induce denial-of-service (DoS) conditions. Given the high cost and limited availability of likely trustworthy quantum hardware, users may be enticed to explore emerging and trust-seeking but cheaper and readily available quantum hardware, which can enable the stealth of IP and tampering of quantum programs and/or computation outcomes. Similarly, emerging compilation services may compromise circuit confidentiality or insert Trojans. Despite the strategic significance of QC and its potential to process sensitive information, its security and privacy concerns remain underexplored. This article presents a comprehensive overview of QC fundamentals, key vulnerabilities, recent attack vectors, and corresponding defenses, and concludes with directions for future research to strengthen the quantum security community.

Quantum computing has proven to be capable of accelerating many algorithms by performing tasks that classical computers cannot. As quantum algorithms and implementations grow more complex, the need for rigorous circuit verification becomes critical, ensuring correct compilation and enhancing circuit fidelity through error correction and assertions. In this paper, we propose QuBEC, a Decision Diagram-based quantum equivalence checking approach, that requires less latency compared to existing techniques, while accounting for circuits with quantum error correction redundancy. QuBEC reduces verification time on benchmark circuits by up to 443×, while the number of Decision Diagram nodes required is reduced by up to 798.31×, compared to state-of-the-art strategies. The proposed QuBEC framework can contribute to the advancement of quantum computing by enabling faster and more efficient verification of quantum circuits, paving the way for the development of larger and more complex quantum algorithms.

Trapped-ion systems can have a limited number of ions (qubits) in a single trap. Increasing the qubit count to run meaningful quantum algorithms would require multiple traps where ions need to shuttle between traps to communicate. The existing compiler has several limitations, which result in a high number of shuttle operations and degraded fidelity. In this paper, we target this gap and propose compiler optimizations to reduce the number of shuttles. Our technique achieves a maximum reduction of 51.17% in shuttles (average ~ 33%) tested over 125 circuits. Furthermore, the improved compilation enhances the program fidelity up to 22.68X with a modest increase in the compilation time.

Trapped-ion (TI) quantum computer is one of the forerunner quantum technologies. Execution of a quantum gate in multiple trap TI system may frequently involve ions from two different traps, hence one of the ions needs to be shuttled (moved) between traps to be co-located, degrading fidelity, and increasing the program execution time. The choice of initial mapping influences the number of shuttles. The existing Greedy policy neglects the depth of the program at which a gate is present. Intuitively, the contribution of the late-stage gates to the initial mapping is less since the ions might have already shuttled to a different trap to satisfy other gate operations. In this paper, we target this gap and propose a new program adaptive policy especially for programs with considerable depth and high number of qubits (valid for practical-scale quantum programs). Our technique achieves an average reduction of 9% shuttles/program (with 21.3% at best) for 120 random circuits and enhances the program fidelity up to 3.3X (1.41X on average).

Quantum computing is a rapidly expanding field with applications ranging from optimization all the way to complex machine learning tasks. Quantum memories, while lacking in practical quantum computers, have the potential to bring quantum advantage. In quantum machine learning applications for example, a quantum memory can simplify the data loading process and potentially accelerate the learning task. Quantum memory can also store intermediate quantum state of qubits that can be reused for computation. However, the depth, gate count and compilation time of quantum memories such as, Quantum Read Only Memory (QROM) scale exponentially with the number of address lines making them impractical in state-of-the-art Noisy Intermediate-Scale Quantum (NISQ) computers beyond 4-bit addresses. In this paper, we propose techniques such as, pre-decoding logic and qubit reset to reduce the depth and gate count of QROM circuits to target wider address ranges such as, 8-bits. The proposed approach reduces the number of gates and depth count by at least 2X compared to the naive implementation at only 36% qubit overhead. A reduction in circuit depth and gate count as high as 75X and compilation time by 85X at the cost of a maximum of 2.28X qubit overhead is observed. Experimentally, the fidelity with the proposed pre-decoding circuit compared to existing optimization approach is also higher (as much as 73% compared to 40.8%) under reduced error rates.

Present-day quantum computers suffer from various noises or errors such as, gate error, relaxation, dephasing, readout error, and crosstalk. Besides, they offer a limited number of qubits with restrictive connectivity. Therefore, quantum programs running these computers face resilience issues and low output fidelities. The noise in the cloud-based access of quantum computers also introduce new modes of security and privacy issues. Furthermore, quantum computers face several threat models from insider and outsider adversaries including input tampering, program misallocation, fault injection, Reverse Engineering (RE) and Cloning. This paper provides an overview of various assets embedded in quantum computers and programs, vulnerabilities and attack models and the relation between resilience and security. We also cover countermeasures against the reliability and security issues and present future outlook for security of quantum computing.

An efficient quantum circuit (program) compiler aims to minimize the gate-count - through efficient instruction translation, routing, gate, and cancellation - to improve run-time and noise. Therefore, a high-efficiency compiler is paramount to enable the game-changing promises of quantum computers. To date, the quantum computing hardware providers are offering a software stack supporting their hardware. However, several third-party software toolchains, including compilers, are emerging. They support hardware from different vendors and potentially offer better efficiency. As the quantum computing ecosystem becomes more popular and practical, it is only prudent to assume that more companies will start offering software-as-a-service for quantum computers, including high-performance compilers. With the emergence of third-party compilers, the security and privacy issues of quantum intellectual properties (IPs) will follow. A quantum circuit can include sensitive information such as critical financial analysis and proprietary algorithms. Therefore, submitting quantum circuits to untrusted compilers creates opportunities for adversaries to steal IPs. In this paper, we present a split compilation methodology to secure IPs from untrusted compilers while taking advantage of their optimizations. In this methodology, a quantum circuit is split into multiple parts that are sent to a single compiler at different times or to multiple compilers. In this way, the adversary has access to partial information. With analysis of over 152 circuits on three IBM hardware architectures, we demonstrate the split compilation methodology can completely secure IPs (when multiple compilers are used) or can introduce factorial time reconstruction complexity while incurring a modest overhead (~ 3% to ~ 6% on average).

Quantum approximate optimization algorithm (QAOA) is a promising quantum-classical hybrid algorithm to solve hard combinatorial optimization problems. The two-qubits gates used in quantum circuit for QAOA are commutative i.e., the order of gates can be altered without changing the logical output. This re-ordering leads to execution of more gates in parallel and a smaller number of additional gates to compile the QAOA circuit resulting in lower circuit depth and gate-count which is beneficial for circuit run-time and noise. A lower number of gates means a lower accumulation of gate errors, and a lower circuit depth means the quantum bits will have a lower time to decohere (lose state). However, finding the best re-ordered circuit is a difficult problem and does not scale well with circuit size. This paper presents a compilation flow with 3 approaches to find an optimal re-ordered circuit with reduced depth and gate count. Our approaches can reduce gate count up to 23.21% and circuit depth up to 53.65%. Our approaches are compiler agnostic, can be integrated with existing compilers, and scalable.

We propose a machine learning based approach to accelerate quantum approximate optimization algorithm (QAOA) implementation which is a promising quantum-classical hybrid algorithm to prove the so-called quantum supremacy. In QAOA, a parametric quantum circuit and a classical optimizer iterates in a closed loop to solve hard combinatorial optimization problems. The performance of QAOA improves with increasing number of stages (depth) in the quantum circuit. However, two new parameters are introduced with each added stage for the classical optimizer increasing the number of optimization loop iterations. We note a correlation among parameters of the lower-depth and the higher-depth QAOA implementations and, exploit it by developing a machine learning model to predict the gate parameters close to the optimal values. As a result, the optimization loop converges in a fewer number of iterations. We choose graph MaxCut problem as a prototype to solve using QAOA. We perform a feature extraction routine using 100 different QAOA instances and develop a training data-set with 13, 860 optimal parameters. We present our analysis for 4 flavors of regression models and 4 flavors of classical optimizers. Finally, we show that the proposed approach can curtail the number of optimization iterations by on average 44.9% (up to 65.7%) from an analysis performed with 264 flavors of graphs.

Quantum approximate optimization algorithm (QAOA) is a promising quantum-classical hybrid algorithm to solve hard combinatorial optimization problems using noisy quantum devices. The multiqubit CPHASE gates used in the quantum circuit for QAOA are commutative i.e., the order of the gates can be altered without changing the output state. This re-ordering leads to the execution of more gates in parallel and a smaller number of additional SWAP gates to compile the QAOA circuit resulting in lower circuit-depth and gate-count. A less number of gates generally indicates a lower accumulation of gate-errors, and a reduced circuit-depth means less decoherence time for the qubits. However, near-term quantum devices exhibit significant variations in the gate success probabilities. Variation-aware compilation policies (i.e. putting most gate operations on qubits with higher gate success probabilities) can enhance the probability of successful program execution on the hardware. The greater flexibility of QAOA-circuits offer better scope of optimization with QAOA-tailored compilation policies. This paper presents an argument for compilation policies to exploit the unique characteristics of QAOA-circuits alongside the variation-awareness of the noisy devices. We present two procedures - variation-aware qubit placement (VQP) and variation-aware iterative mapping (VIM) that can improve the circuit success probability quite significantly (≈8.408X on average) for a set of QAOA-MaxCut problems on ibmq_16_melbourne.

The noisy intermediate-scale quantum (NISQ) computers suffer from unwanted coupling across qubits referred to as crosstalk. Existing literature largely ignores the crosstalk effects which can introduce significant error in circuit optimization. In this work, we present a crosstalk modeling analysis framework for near-term quantum computers after extracting the error-rates experimentally. Our analysis reveals that crosstalk can be of the same order of gate error which is considered a dominant error in NISQ devices. We also propose adversarial fault injection using crosstalk in a multiprogramming environment where the victim and the adversary share the same quantum hardware. Our simulation and experimental results from IBM quantum computers demonstrated that the adversary can inject fault and launch a Denial-of-Service attack. Finally, we propose system- and device-level countermeasures.

Variational algorithm using Quantum Approximate Optimization Algorithm (QAOA) can solve the prime factorization problem in near-term noisy quantum computers. Conventional Variational Quantum Factoring (VQF) requires a large number of 2-qubit gates (especially for factoring a large number) resulting in deep circuits. The output quality of the deep quantum circuit is degraded due to errors limiting the computational power of quantum computing. In this paper, we explore various transformations to optimize the QAOA circuit for integer factorization. We propose two criteria to select the optimal quantum circuit that can improve the noise resiliency of VQF.

The quantum approximate optimization algorithm (QAOA) is a promising quantum-classical hybrid algorithm to solve hard combinatorial optimization problems. The multi-qubit CPHASE gates used in the quantum circuit for QAOA are commutative i.e., the order of the gates can be altered without changing the output state. This re-ordering leads to the execution of more gates in parallel and a smaller number of additional SWAP gates to compile the QAOA-circuit. Consequently, the circuit-depth and cumulative gate-count become lower which is beneficial for circuit execution time and noise resilience. A less number of gates indicates a lower accumulation of gate-errors, and a reduced circuit-depth means less decoherence time for the qubits. However, finding the best-ordered circuit is a difficult problem and does not scale well with circuit size. This paper presents four generic methodologies to optimize QAOA-circuits by exploiting gate re-ordering. We demonstrate a reduction in gate-count by ≈23.0% and circuit-depth by ≈53.0% on average over a conventional approach without incurring any compilation-time penalty. We also present a variation-aware compilation which enhances the compiled circuit success probability by ≈62.7% for the target hardware over the variation unaware approach. A new metric, Approximation Ratio Gap (ARG), is proposed to validate the quality of the compiled QAOA-circuit instances on actual devices. Hardware implementation of a number of QAOA instances shows ≈25.8% improvement in the proposed metric on average over the conventional approach on ibmq 16 melbourne.

Concerted efforts by the academia and the industries e.g., IBM, Google and Intel have brought us to the era of Noisy Intermediate-Scale Quantum (NISQ) computers. Qubits, the basic elements of quantum computer, have been proven extremely susceptible to different noises. Recent experiments have exhibited spatial variations among the qubits in NISQ hardware. Therefore, conventional mapping of qubit done without quality awareness results in significant loss of fidelity for a given workload. In this paper, we have analyzed the effects of various noise sources on the overall fidelity of the given workload for a real NISQ hardware. We have also presented novel optimization technique namely, Qubit Re-allocation (QURE) to maximize the sequence fidelity of a given workload. QURE is scalable and can be applied to future large scale quantum computers. QURE can improve the fidelity of a quantum workload up to 1.54X (1.39X on average) in simulation and up to 1.7X in real device compared to variation oblivious qubit allocation without incurring any physical overhead.

Rapid advancement in the domain of quantum technologies have opened up researchers to the real possibility of experimenting with quantum circuits, and simulating small-scale quantum programs. Nevertheless, the quality of currently available qubits and environmental noise pose a challenge in smooth execution of the quantum circuits. Therefore, efficient design automation flows for mapping a given algorithm to the Noisy Intermediate Scale Quantum (NISQ) computer becomes of utmost importance. State-of-the-art quantum design automation tools are primarily focused on reducing logical depth, gate count and qubit counts with recent emphasis on topology-aware (nearest-neighbour compliance) mapping. In this work, we extend the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives. We provide a comprehensive problem formulation and multi-tier approach towards solving it. The proposed automation flow is compatible with commercial quantum computers, such as IBM QX and Rigetti. Our simulation results over 10 quantum circuit benchmarks, show that the fidelity of the circuit can be improved up to 3.37 × with an average improvement of 1.87 ×.

Emerging non-volatile memory (NVM) technologies are being aggressively explored to replace and/or assist conventional CMOS technology. Although NVMs can cut down leakage power, achieve low footprint and allow compute capability along with storage, they suffer from new sources of variability. We review the noise sources associated with NVMs and describe resilience enhancement techniques for both memory and computing. We also present security applications where noise and variability is desirable.

The public access to noisy intermediate-scale quantum (NISQ) computers facilitated by IBM, Rigetti, D - Wave, etc., has propelled the development of quantum applications that may offer quantum supremacy in the future large-scale quantum computers. Parameterized quantum circuits (P QC) have emerged as a major driver for the development of quantum routines that potentially improve the circuit's resilience to the noise. PQC's have been applied in both generative (e.g. generative adversarial network) and discriminative (e.g. quantum classifier) tasks in the field of quantum machine learning. PQC's have been also considered to realize high fidelity quantum gates with the available imperfect native gates of a target quantum hardware. Parameters of a P QC are determined through an iterative training process for a target noisy quantum hardware. However, temporal variations in qubit quality metrics affect the performance of a P QC. Therefore, the circuit that is trained without considering temporal variations exhibits poor fidelity over time. In this paper, we present training methodologies for P QC in a completely classical environment that can improve the fidelity of the trained P QC on a target NISQ hardware by as much as 21.91%.

Analog Integrated Circuits (ICs) are one of the top targets for counterfeiting. However, the security of analog Intellectual Property (IP) is not well investigated as its digital counterpart. In this paper, we explore the possibility of multi-threshold voltage (VTH) design to protect the analog IP from Reverse Engineering (RE)-based attacks. Analog circuits are sensitive to VTH as the operating region of a transistor can vary with VTH. Furthermore, the VTH of individual transistors cannot be identified during the RE process. The trial-and-error based technique to guess the VTH and validate with a golden IC will ramp up RE effort exponentially. Thus, by carefully including multi-VTH transistors, the designer can ensure that the properties of analog IP e.g., gain, bandwidth, and linearity are protected even though the physical dimensions of the transistors are revealed. We demonstrate this technique by using a case study on a wide-swing cascode amplifier. Simulations show that incorrect VTH inference can lead to substantially degraded performance like 98 dB drop in open-loop gain and up to 19% increase in total harmonic distortion. Based on VTH choice, the proposed technique can save ~ 3% area over conventional design. We show that the reverse engineering effort can be ~1013 years. We propose a technique like transistor splitting to increase the effort even more. Mismatch analysis shows that the proposed technique results in only 1% loss in mean robustness.