This article proposes implementation-friendly Gerschgorin radii and center ratio (GRCR)-based cooperative spectrum sensing (CSS) algorithm with reduced computational complexity that delivers adequate performance in uniform- and nonuniform-dynamical noise-and-received signal power scenarios. Subsequently, a new VLSI architecture of cooperative spectrum sensor (CSR) based on the proposed GRCR algorithm and additional architectural optimization has been suggested that consumes lower area and delivers shorter sensing time. Performance analysis of our implementation-friendly GRCR-based CSS algorithm has been carried out under the Rayleigh fading channel, and it delivers adequate area under the receiver-operating-characteristic (ROC) curve (AUC) = 0.9 at an average signal-to-noise ratio (SNRavg) of −5 dB. Consecutively, an application-specific integrated circuit (ASIC) chip of the proposed CSR has been fabricated in the UMC 130-nm CMOS process. It occupies 0.27 mm2of the core area, and its maximum operating frequency is 88.8 MHz at 1.2 V of the supply voltage. At this clock frequency, our CSR delivers a sensing time of$5~\mu \text{s}$while processing the received signal samples from four secondary users in a cognitive-radio network. These ASIC-implementation results are compared with the reported works in the literature where our design has shown$45\times $and$12\times $better hardware efficiency and sensing time, respectively, compared to the state-of-the-art implementations.

Spectrum sensing is an imperative process that primarily affects the reliability of cognitive radio networks (CRNs). Cooperative spectrum sensing (CSS) is the contemporary process of detecting the occupancy of spectrum by licensed users in CRN. It outperforms the conventional stand-alone spectrum-sensing (SSS) algorithms. However, such CSS algorithms have higher implementation-complexity than SSS algorithms, resulting in higher resource utilization and alleviating the hardware efficiency. Our work focuses on the design of hardware efficient VLSI-architecture for such CSS algorithms. Specifically, this paper proposes reconfigurable VLSI-architecture of cooperative spectrum sensor (CSR) for both maximum-minimum eigenvalue (MME) and maximum eigenvalue (MED) based CSS algorithms for the data-fusion based CRN. This CSR architecture has been designed based on iterative and shift power-methods to compute maximum and minimum eigenvalues in MME and MED CSS-algorithms. The proposed reconfigurable-CSR is fabricated in UMC 130-nm CMOS process and it has a die dimension of h × w =3D 1.5 mm × 1.5 mm. Furthermore, this work presents the analysis of hardware-complexity, sensing-time and performance with the increasing number of secondary users (or antenna array of CSR) in CRN. Eventually, the fabricated ASIC chip of CSR has been tested and verified in a real-world test environment.

This article presents a hardware-friendly algorithm and architecture for cooperative spectrum sensing (CSS) in the data-fusion-based cognitive-radio (CR) network. The proposed VLSI-algorithm is based on the iterative power method and deflation technique that alleviate the computational complexity of conventional CSS algorithm with minimal performance degradation. In this work, a new hardware-efficient VLSI architecture of cooperative spectrum sensor (CSR) for the data-fusion center is presented, which supports up to six secondary users in the cooperative CR network. Its performance analysis under fading channel environment has been carried out where it delivers 0.8 detection probability ( Pd) at -8 dB of channel SNR with a false alarm rate of 0.1. It shows the minimum performance degradation of 0.057 dB at Pd= 0.88 compared to the conventional algorithm. The suggested CSR architecture has been application-specific integrated circuit (ASIC)-synthesized and postlayout simulated in UMC 90 nm-CMOS process. Thus, it occupies 2.4 mm2of the core area, consumes 36 mW of total power, and delivers a low sensing time of 60.41 μs while operating at a maximum clock frequency of 87.7 MHz. Comparison with the reported works indicates that the proposed design requires 40.3% lesser area, and it is 41% hardware efficient than the conventional implementation. Eventually, this design has been field-programmable gate array (FPGA) prototyped, and its functionality is verified in the real-world test environment.

This brief presents new VLSI architecture of spectrum sensor based on maximum eigenvalue based detection (MED) algorithm for cognitive radio applications. Our contributions focus on the formulation of hardware friendly MED based spectrum sensing algorithm. In addition, we propose resource-shared VLSI architecture for this algorithm to further enhance the hardware efficiency and lower the sensing time. Performance comparison of MED and cyclostationary based spectrum sensing algorithms has been carried out in AWGN channel environment using OFDM modulation and demodulation where the MED based spectrum sensing algorithm delivered better performance than cyclostationary based spectrum sensing by 4.5 dB at the detection probability of 0.5. We have synthesized and post-layout simulated our spectrum sensor in UMC 90 nm-CMOS process. Thus, it occupies 0.42 mm2of core area and operates at maximum clock frequency of 406 MHz resulting in a sensing time of90%.

Hardware implementation of Floating Point Units (FPUs) has been a key area of research due to their massive area and energy footprints. Recently, a proposal was made to replace IEEE 754-2008 technical standard compliant FPUs with Posit Arithmetic Units (PAUs) due to the greater accuracy, speed, and simpler hardware design. In this paper, we present the architecture of a parameterized PAU generator that can generate PAU adders and PAU multipliers of any bit-width pre-synthesis. We synthesize generated arithmetic units using the parameterized PAU generator for 8-bit, 16-bit, and 32-bit adders and multipliers and compare them with IEEE 754-2008 compliant adders and multipliers. Both, synthesis for Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) are performed. In our comparison of m-bit PAU units with n-bit IEEE 754-2008 compliant units, it is observed that the area and energy of a PAU adder and multiplier are comparable to their IEEE 754-2008 compliant counterparts where m=n. We argue that an n-bit IEEE 754-2008 adder and multiplier can be safely replaced with an m-bit PAU adder and multiplier where m