This paper describes a low-cost technique for extracting parameters of interest for test boards used in multisite automatic test equipment (ATE). In the proposed approach, physical elements and nets on the PCB are represented as a graph with nodes and edges. Graph traversal algorithms are then used to extract data about the connections between specific components on each test site. This approach automates the previously slow and manual process of generating the topology files necessary to extract board parameters. The proposed method is implemented on a multisite test board, and results are presented.

Multisite (parallel) testing is becoming more widely used in analog and mixed-signal testing to increase throughput and meet high customer demand. However, site-to-site variations are inevitable due to the complexities involved in massive multisite test board design. Sites with pronounced systematic errors (issue sites) lead to measurements not reflecting the true performance of the device under test (DUT), causing potential yield loss and test escapes. Traditional mechanical repair of such sites is expensive, time-consuming, and labor-intensive. Polynomial transformation methods have been successfully explored to calibrate measurements at issue test sites. However, its rigid application could lead to overfitting or underfitting without foreknowledge of the nature and level of induced errors. This paper presents an optimal order polynomial transformation method that is flexible and self-adaptive. It uses a predefined error metric to find the optimal-order of the transformation polynomial and provides optimal calibration coefficients. Simulations and real test data are used to evaluate the effectiveness of the proposed method. Further validation is also provided by comparing the die measurements of issue sites after calibration against a more accurate reference.

The multisite test hardware is built with imperfect elements. Hence, like all measuring instruments, measurement errors are induced by test sites. These errors (random and systematic) are usually insignificant to guarantee test quality. However, as the number of test sites on the multisite tester increases (to further increase throughput), the induced systematic errors for some test sites become pronounced. The measurements of some test sites no longer reflect the true performance of the device under test (DUT), and the likelihood of yield loss or potential test escapes is increased. While multisite test hardware troubleshooting and correction can be difficult, time-consuming, and expensive, it is much easier to calibrate the measurements of issue sites (test sites with unacceptable systematic variations). This paper proposes a least-squares method for systematic hardware error identification and calibration. This method uses linear regression to compare the distribution of measurements at each test site to that of a reference (true and expected) distribution as a means to identify systematic errors and calibrate them. This approach provides a practical black box technique to mitigate test hardware systematic variations and further guarantee test quality. MATLAB® experiments indicate our approach outperforms existing methods in terms of accuracy. Application of the method to real test data confirms the effectiveness and robustness of the method without compromising test quality.

Multisite testing has become a proven method to reduce test time and costs for integrated circuits (IC). However, the technique suffers from site-to-site variations, especially when a large number of test sites are involved. It becomes imperative to identify issue sites that exhibit unacceptable variations to prevent yield loss or incorrect passing of faulty devices. By correctly identifying the true probability distribution of tested specifications, identification of issue sites becomes easier. We introduce an ordinal optimization-based algorithm to select the right sites to estimate the true distribution in situations where it is difficult or impossible to find the true distribution for tested specifications. Using both simulation and real-world ATE test data, we demonstrate that this approach yields good results.

Multisite testing significantly increases throughput by testing multiple chips simultaneously. When implemented on a large scale (massive multisite), the complex signal routing involved, interference, and coupling on the test hardware (amongst other issues) often affect test sites differently, introducing variations in site measurements. We hypothesize in this paper that each test site’s measurement can be modeled as a weak nonlinear function of the true chip measurement with systematic errors. We propose an algorithm to detect these systematic errors and calibrate them. This approach provides a practical black box technique to mitigate test hardware variations while investigating the fundamental root causes. The proposed method is verified with simulation and real test data.

Multi-site testing saves test time and tests cost by screening multiple chips at once. However, it comes with its issues. As test engineers increase the number of sites on each tester to further save test time and cost, variations are now being observed in measurements from site to site which do not correspond to actual problems in the devices under test. Thus, a cost-effective way to investigate site to site variations and identify sites with issues needs to be developed to ensure high test quality and to rule out possible problems arising from the test hardware. In this paper, regression fitting on a quantile-quantile curve is used to compare the distribution of each site to a theoretical and expected distribution. This is shown to pronounce site to site variations inherent in test data, hence identifying issue-ridden sites with ease. The quantile-quantile plot compares the integrals of two probability density functions in a single plot, thus capturing the location, scale, and skewness of the test data set. This method provides more information to the test engineer than classical statistical methods that rely on single test statistics for distribution comparison and is at no extra cost.

Production test of parametric specifications is a significant contributor to the overall cost of build for analog and mixed-signal products. Data converters (ADCs and DACs) in particular are critical components of integrated circuits used in control/actuation and sensing applications. If left un-optimized, their production test time often dominates the overall system-on-chip (SoC) test time. In this paper, we specifically focus on static linearity test of DACs and propose architecture-aware test methods that are combined with best-in-class fast linearity test concepts in the literature to minimize test time without compromising test quality. The proposed methods exploit the hypothesis that the number of device errors which contribute to linearity errors can be captured by a significantly fewer number of variables than the number of codes at which linearity needs to be tested. We introduce a new time and memory efficient method called Extrapolated Reconstruction (ER) to calculate DAC INL and DNL, based on the segmented model introduced in uSMILE. We also demonstrate that since the segmented model techniques do not account for interpolation, they are not suitable for interpolated DACs. We thus develop an interpolated segmented model and enhance both uSMILE and ER to obtain two new methods that provide correct estimations for interpolated DACs. A linearity test time reduction of 15×-20× was seen in actual silicon measurement results for multiple 12-bit DACs and >100× was seen in simulation case studies for many 16-bit DACs.