Andleeb Zahra

dblp:234/3152 · DBLP profile ↗
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7ranked-venue papers
0as first author
7since 2021 · last 2026
0009-0006-8114-5544ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 7 · 7 since 2021
YearPublicationVenuePosition
2026 Low Supply, Impedance-Boosted Current Mirror Using Back-Gate in FD-SOI Technology
Roopesh G. L, Arpan Jain, Soham Bhattacharyya, Ashfakh Huluvallay, Andleeb Zahra, Zia Abbas
ISCAS5
2026 A 0.5V 72-pW Process and Temperature Compensated Voltage Reference
Vikkram Srinivasan, Damini Chandi Priya A, Ashfakh Huluvallay, Arpan Jain, Abhishek Pullela, Andleeb Zahra, Zia Abbas
ISCAS6
2025 C-Arch: Chained Architecture towards Foundation Modeling of CMOS/FinFET Circuit Designs
abstract
Modeling process, operating condition, reliability, and technological variation in transistor level design introduce significant variance in device and performance parameters. This paper presents a machine-learning-based architectural approach that enhances model performance, as a step towards developing Foundation Models tailored for circuit data, accurately capturing technology and process-induced variations in leakage power, voltage, and current. The architecture incorporates the impact of varying operating conditions, including temperatures from -55°C to 125°C and supply voltage fluctuations of ±10% on 16nm HP FinFET, and 16nm, 22nm, 32nm, and 45nm HP-MGK CMOS technology nodes. By enhancing the performance of baseline machine-learning models using a chained architecture to cater to the high variance in target, our C-Arch serves as a versatile framework for circuit modeling when the data spread is high. Experimental results on current, voltage, and leakage power estimation, demonstrate average improvements of up to 93.76%, 96.17%, and 88.82% in Mean Absolute Percentage Error compared to baseline models, underscoring the computational savings and viability of Foundation Models in circuit design.
Ritwik Basyas Goswami, Mohammad Rehan Akhtar, Andleeb Zahra, Zia Abbas
ISCAS3
2024 An inductor-less, cost-effective On-chip CMOS VNA for bio-molecule detection
abstract
Biomolecules play indispensable roles in all life processes, including disease development, so their accurate detection is critical to cell investigation, medical diagnosis, and treatment. Radio Frequency (RF) sensing has become a popular testing technique compared to traditional methods for biomolecule analysis, providing results in less time using less volume of samples. It allows rapid, sensitive, real-time measurements and label-free techniques. However, for taking the signals from biomolecules over the RF-based sensors we need to connect them with the Vector Network Analyzer (VNA) which is a bulky and costly device. To develop an RF sensing based a true lab-on-chip (LoC) device, the paper presents a fully integrated low-power less-area on-chip single port CMOS VNA designed in 65nm CMOS technology to detect the bio-molecule The proposed design works in a tunable frequency range of 0.5 GHz to 2.5 GHz, ensuring much higher precision. Using an RLC equivalent of an Interdigitated capacitor (IDC) sensor, a fully integrated architecture for detecting S11of the biomolecules has been introduced. A resistive bridge coupler is used for wideband operation with a directivity of 14.89dB up to 2.5 GHz. Also, a high-linearity LNA (low noise amplifier) is designed with a linearity of -13dB and a gain of 14dB. The LNA has a low NF of 3.21dB. The design occupies an active area of 0.01767mm2and consumes power of 41mW from a 1 V supply.
Bhartipudi Sahishnavi, Samriddhi Agarwal, Shameer Basha Yerragudi, Naveen Dasari, Andleeb Zahra, Prabhakar Bhimalapuram, Syed Azeemuddin, Zia Abbas
ISCAS5
2023 Approximate Toom-Cook FFT with sparsity aware error tuning in a shared memory architecture
Mohammed Salman Ahmed 0002, Md. Kalesha, Andleeb Zahra, Zia Abbas
Integr.3
2023 AI/ML algorithms and applications in VLSI design and technology
Deepthi Amuru, Andleeb Zahra, Harsha V. Vudumula, Pavan K. Cherupally, Sushanth R. Gurram, Amir Ahmad, Zia Abbas
Integr.2
2021 Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations
abstract
In this paper, we aim at optimizing the leakage power and propagation delays using optimization algorithms like Glowworm Swarm Optimization and Neighbourhood Cultivation Genetic Algorithm, subjected to variations in Process, Voltage, Temperature and Aging degradation (PVTA) targeting low power or high performance applications. For high performance applications, we synthesize transistor sizes, at which the critical path delay in worst case PVT conditions with 3 years of NBTI aging degradation is optimized below the critical path delay (of initial sizing) at nominal conditions keeping power budget in bound. On the other hand, for low power applications, we obtain transistor sizing where leakage is reduced by more than 50%, keeping a bound on critical path delay. All the pre and post stress simulations are performed using HSPICE for 22nm Metal Gate High-K dielectric model parameters. The temperature range and the supply voltage ranges are -55 °C to 125 °C and 0.72V to 0.88V respectively. The process parameters are considered at ±3σ variation. The ingenuous working of the circuits for the obtained sizing is ensured by Monte Carlo analysis evaluating over entire range of process variations and operating conditions for intended life time.
Hema Sai Kalluru, Prasenjit Saha, Andleeb Zahra, Zia Abbas
ISCAS3