In this paper, a cost-effective and easy-to-implement auto-trim technique is introduced for PTAT or CTAT resistance based current references. The resistance with a process-insensitive temperature coefficient requires only a single point trim at room temperature, achieving process and temperature-insensitive current. The approach utilizes a data comparison method where on-chip current data is compared with off-chip reference data to trim the resistance of the current reference. The off-chip reference data is generated using a low-cost external resistor that is used only during the trimming operation. The proposed trimming sensor effectively calibrates the current, offering precision close to manual trimming, leading to cost, time, and resource savings. To validate the working of the proposed technique, the auto trim sensor with on-chip current reference is designed in TSMC 180nm technology. The auto trim sensor calibrates the on-chip current from ±25% (due to voltage and resistance process variation) to ±1.5% across the process and 3σ mismatch.

This paper proposes a 162nW resistance-to-digital converter (RDC) for miniature battery-powered sensing systems. The RDC first converts input resistance to a pulse by charging a capacitor to a threshold voltage with a current proportional to the resistance. It compensates temperature sensitivity of the charging current by generating the threshold voltage with the same temperature dependency. Then, the circuit digitizes the pulse using an up-down counter that cancels temperature-dependent delay and offset of the low-power comparator in a digital Correlated Double Sampling (CDS) style. Designed in a 180 nm CMOS process, the proposed circuit achieves a figure-of-merit (FoM) of 0.845pJ/c.s. in simulation, with a conversion time of 50 ms for input resistance from$50\mathrm{k}\Omega$to$1\mathrm{M}\Omega$, while consuming 162nW at a supply voltage of 900 mV. Also, it obtains a temperature sensitivity of 26.9ppm/°C from −40 to 100°C. Compared with the state-of-the-art RDCs, this work improves the FoM and temperature sensitivity by 42.91% and 11.52%, respectively.

The paper presents a novel nW range gate-leakage-based Sub-Bandgap Voltage Reference (sub-BGR) for low-power and high-temperature range IoT applications. It generates a reference voltage of 336mV without incorporating any resistors and operating for a high-temperature range of −40°C to 150°C and a supply range of 0.7V-4V. In the above temperature and supply ranges, the proposed circuit's power consumption only goes up by 30x and 1.025x times, respectively. Designed in a 65nm CMOS process, the proposed architecture achieves an accuracy of 94ppm/°C. It achieves a line sensitivity of 0.0066%/V for a supply range of 0.7V to 4V and a PSRR of 89dB at DC and 1V supply. The proposed circuit shows$\mathrm{a}\pm 3\sigma$-inaccuracy of 4.295% without additional trimming circuits. It occupies only 0.0851mm2 area while consuming only 2.3nW at 27°C and 21.74nW at 150°C for a 0.7V supply.

The paper presents a 0.5V supply, gate leakage-based current/voltage reference for ultra-low power IoT and biomedical applications. The references are generated by the proper addition of PTAT and CTAT curves, which are obtained by exploiting the traditional architecture of the beta multiplier and using the body biasing effect. Gate leakage transistors replace the resistors to ensure low power and low area. The circuit doesn't involve any Op-Amps avoiding the issues of offset that are prominent in these circuits. Implemented in CMOS 90nm technology, the proposed current (voltage) reference achieves a typical accuracy of$34.6\text{ppm} /{ }^{\circ} \mathrm{C}(29.68 \text{ppm} /{ }^{\circ} \mathrm{C})$over a wide temperature range of$-55^{\circ} \mathrm{C}$to$75^{\circ}\mathrm{C}$with typical value 63.32pA(0.35V). Excellent line sensitivity of 0.0318%N and 0.0576%N are observed for voltage and current reference, respectively, in a supply range of 0.5V - 2.3V. The area occupied by the total circuit is 0.0096mm2, while the power consumption is 415pW at the typical corner of$27^{\circ}C$and 0.5V supply.

The paper presents a sub-nW gate-leakage based voltage and current reference in a single circuit whose reference values are scalable and doesn’t incorporate start-up circuits or resistors in the architecture. The power consumption of the proposed circuit increases by only 2.1x in the temperature range of -55°C to 100°C, unlike conventional voltage/current references where the power consumption increases exponentially w.r.t temperature. Implemented in 90nm technology, the proposed voltage reference (current reference) achieves post-trim typical accuracy of 22ppm/°C(58ppm/°C) and worst-case accuracy of 71ppm/°C(78ppm/°C). Excellent line sensitivities of 0.029%/V and 0.059%/V are observed for voltage and current reference respectively, in a supply range of 1V - 3V. Without any start-up circuit, the observed 99% settling times for voltage and current reference are 1.92ms and 2.526ms respectively. The area occupied by the total circuit is 0.0015mm2, while the power consumption is 156pW at typical corner, 27°C and 1V supply.

The paper presents a sub-nW BJT based temperature sensor for ultra-low power microsystems. The sensor is based on amplifying the difference between base-emitter voltages of BJTs using gate-leakage transistors. Implemented in UMC 65nm technology, the sensor occupies an area of 0.005mm2. It achieves a maximum non-linearity error of 0.12oC(3σ) over the temperature range of - 55oC to 80oC. Without any trimming, a worst case inaccuracy of +0.36oC/ - 1.61oC is observed w.r.t process variations, depicting the process-invariant nature of the temperature sensor. It also achieves a low supply sensitivity of 0.56oC/V over a wide supply range of 0.7V-3V. The power consumption of the sensor is 419pW at 27oC and 0.7V supply.

In this paper, a highly stable all CMOS current reference against temperature and supply variation is proposed. Current reference of 5μA and 50nA has been designed for low power and ultra-low power applications respectively. The reference architecture is based on ratio between the PTAT voltage and the PTAT resistance. The process insensitive temperature compensation is accomplished by dividing TC of voltage with process insensitive TC of resistor. A high PSRR, process independent voltage reference is designed for PTAT voltage. N-poly on chip resistor is used for PTAT resistance. The proposed current reference is implemented in 0.18-μm TSMC technology. The architecture achieved PSRR of 74dB and line sensitivity of 0.05% works at supply voltage variation from 1.4V to 3.6V. The current reference of 5μA and 50nA attain temperature coefficient of 11.6 ppm/°C and 12.2 ppm/°C respectively for the temperature variation of -55° C to 125° C.

A sub 1-V, ultra low power temperature sensor has been implemented in TSMC 180 nm. The architecture is digital friendly since it creates a pulse width modulated wave instead of voltage. It uses proportional to absolute temperature(PTAT) characteristics of resistance to generate PTAT delay. Temperature to delay conversion depends only on passive elements, thereby making the circuit insensitive to supply variations. Line sensitivity of 0.23 °C/V is achieved for a wide supply range of 0.7-3.6V. A non linearity error of less than 0.8 °C is measured for -55 to 125 °C using linear fit curve. This occupies an area of 0.82 mm2and consumes a power of 47 nW at 0.8 V supply.