Intelligent reflecting surface (IRS) is one of the promising technologies for next-generation communication systems. Although IRS can enhance the integrity of the transmitted signal, however, it requires additional phase-shift optimization task, potentially increasing the total processing latency of the system. To implement a phase-shift optimization algorithm with low-latency, for the world-first, IRS controller SoC for saving the base station (BS) transmit (TX) antenna power is presented with novel latency reduction techniques; 1) grid-based phase-shift elements with a coarse-grained update, 2) quality-aware approximate processing element with low-resolution saturation arithmetic, 3) optimized data-flow scheduling with double-buffer architecture, and 4) novel low-latency weight update tracking technique. By adopting the proposed techniques, the fully-optimized SoC architecture can enhance the processing latency and energy consumption by 93% and 68%, respectively, compared with the unoptimized SoC architecture. The proposed system is designed and fabricated in 28 nm CMOS technology, where the implementation results show that the fully-optimized SoC system can achieve 43.9$\mu$s of processing latency while saving 14.5 dB of TX antenna power for optimizing the$16\times 16$grid-based IRS architecture with$128\times 8$MU-MIMO configuration.

In this paper, practical utilization of multiple distributed reconfigurable intelligent surfaces (RISs), which are able to conduct group-specific operations, for multi-group multicasting systems is investigated. To tackle the inter-group interference issue in the multi-group multicasting systems, the block diagonalization (BD)-based beamforming is considered first. Without any inter-group interference after the BD operation, the multiple distributed RISs are operated to maximize the minimum rate for each group. Since the computational complexity of the BD-based beamforming can be too high, a multicasting tailored zero-forcing (MTZF) beamforming technique is proposed to efficiently suppress the inter-group interference, and the novel design for the multiple RISs that makes up for the inevitable loss of MTZF beamforming is also described. Effective closed-form solutions for the loss minimizing RIS operations are obtained with basic linear operations, making the proposed MTZF beamforming-based RIS design highly practical. Numerical results show that the BD-based approach has ability to achieve high sum-rate, but it is useful only when the base station deploys large antenna arrays. Even with the small number of antennas, the MTZF beamforming-based approach outperforms the other schemes in terms of the sum-rate while the technique requires low computational complexity. The results also prove that the proposed techniques can work with the minimum rate requirement for each group.

The number of devices served by baseband stations is constantly increasing due to the rising data traffic in modern communication systems. In order to support large-scale multi-user multiple-input multiple-output (MU-MIMO) systems and achieve their capacity, it is necessary to consider power allocation and user selection along with precoding. This paper introduces a scalable MU-MIMO precoding processor that solves the joint optimization problem for precoding, power allocation, and user selection. We define custom vector instructions and dedicate vector arithmetic operators based on the RV32IM instruction set architecture to efficiently support various MU-MIMO baseband processing scenarios. The proposed vector operators include parallel dual-precision multipliers to enable energy-efficient processing by adjusting the computing resolution of each step without degrading the algorithm-level quality. The proposed processor is fabricated using 28nm CMOS technology and is capable of solving the state-of-the-art joint optimization problem in only 0.51ms for the$64\times 64$large-scale MU-MIMO configuration. Our processor achieves up to 17.4 times higher processing efficiency compared to previous precoder design, even when supporting the largest number of users and the most complicated algorithm.

In order to effectively reduce buffer energy consumption, which constitutes a significant part of the total energy consumption in a convolutional neural network (CNN), it is useful to apply different amounts of energy conservation effort to the different levels of a CNN as the buffer energy to total energy usage ratios can differ quite substantially across the layers of a CNN. This article proposes layerwise buffer voltage scaling as an effective technique for reducing buffer access energy. Error-resilience analysis, including interlayer effects, conducted during design-time is used to determine the specific buffer supply voltage to be used for each layer of a CNN. Then these layer-specific buffer supply voltages are used in the CNN for image classification inference. Error injection experiments with three different types of CNN architectures show that, with this technique, the buffer access energy and overall system energy can be reduced by up to 68.41% and 33.68%, respectively, without sacrificing image classification accuracy.

In this paper, we present a lightweight CNN model named MixNet which is easily scalable to different energy requirements in embedded platforms. The MixNet model uses two extreme bit-precisions that efficiently balances the model accuracy and energy consumption. The energy consumption in processing MixNet is managed by controlling the ratio between high-precision (16bit) and low-precision (1bit) paths. Since only two bit-precisions are required in designing a hardware accelerator, the control logic becomes simpler compared to other multi-precision accelerators. In addition, a reconfigurable multiplier is proposed to enable highly parallel MixNet computations for faster prediction and/or training. Overall, the energy efficiency in terms of run-time per unit power improves by 1.75 ~1.94 × over the recently proposed reduced-precision CNN model.