In this paper, a novel charge pump for sub-sampling phase-locked loops (SSPLLs) is presented. Contrary to the conventional charge pump, the proposed implementation eliminates the previously-required pulser. This is achieved by using all sample data from the ping-pong sub-sampling phase detector as opposed to only every second point, which enables the charge pump to run pseudo-continuous. This virtually raises the reference frequency by a factor of two, which is beneficial for the phase noise performance of the phase-locked loop while fulfilling the requirements for bandwidth of reference buffers, switches etc. Furthermore, eliminating the pulser enables a highly power-efficient charge pump design, leveraging higher SSPLL FoM. The proposed charge pump is implemented in a 22-nm fully-depleted silicon-on-insulator technology. The power and area consumption are reduced by roughly 80% and 55%, with similar effective gain, noise and offset performance to the conventional design.

This paper presents a 12-bit segmented digital-to-analog converter (DAC) with small size high linearity non-cascoded current cells. A pre-distortion calibration technique, using a low-complexity lookup table, is proposed to cancel the third order code-dependent nonlinearity induced by low output impedance of unary current cells. Based on a detailed mathematical analysis, the coefficients of the digital pre-filter are deducted. In addition, the body biasing technique in$22\text{FDX}$technology is employed to adaptively tune the back-gate voltage of each current source via an auxiliary DAC to reduce mismatch errors. The current-steering (CS) DAC achieves >74dBc spurious-free dynamic range (SFDR) and >11 effective number of bits (ENOB) over the entire Nyquist bandwidth at IGS/s and across process and temperature corners. The implementation enables a small area and compact layout of the unary cells, low-power consumption from a dual 0.8/1.2V power supply and a 1-Vppd output signal swing without the use of cascode structures.

This paper presents an overview of the main copper-based automotive Ethernet communication standards, with an emphasis on the existing P802.3ch IEEE standard covering 2.5- 10Gb/s as well as the future P802.3cy standard for up to 50Gb/s full duplex communication. The requirements and key challenges of the automotive physical layer (PHY) are discussed and a 9-bit source series terminated (SST) TX-DAC driver with added echo canceler is proposed for the transmitter. The fabricated TX solution is realized in 22nm FD-SOI technology, and is fully compliant with the P802.3ch standard, proving a lVppd PAM4 output signal, >0.95 RLM while operating up to 11. 2Gb/s. At Nyquist frequency the SFDR is better than 54. 4dBFS while consuming only 2mW/Gb/s per DAC. A bandwidth-extended TX architecture is implemented covering also the P802.3cy standard, which enables PAM-4 signaling up to 14GBaud achieving an SFDR and ENOB of 57. 8dB and 8.1 bit respectively at Nyquist rate.

Orthogonal frequency-division multiplexing (OFDM)-based radars require a high bandwidth for the digital-to-analog (DAC) and analog-to-digital (ADC) converters. Recent advancements in converter designs have pushed the available sampling speed well above 50GS/s. This allows OFDM-based radar waveforms with a high bandwidth to be sampled directly to the carrier frequency, reducing the number of building blocks in the transceiver chain. This paper proposes a CMOS based radar and communication transceiver system design which achieves a range resolution of 10cm and a velocity resolution of 0.55m/s. Utilizing digital I/Q mixing and directly sampling a 1.52GHz bandwidth OFDM-based radar signal halves the number of required data converters and can significantly reduce the I/Q imbalance.