MUX-based logic locking (LL) is a hardware security technique that inserts multiplexers (MUX) into circuits to secure them against unauthorized use and reverse engineering by protecting original circuit pathways. Nevertheless, MUX-based LL is vulnerable to Oracle-Guided (OG) and Oracle-Less (OL) attacks. While OG methods, such as the SAT attack, are infeasible for large-scale designs, OL attacks, like those based on machine learning (ML), can exploit structural leakage in locked circuits to recover original pathways. This study introduces N-MUX, an innovative MUX-based LL approach designed to resist state-of-the-art (SOTA) ML attacks. N-MUX effectively reduces structural leakage by identifying maximal overlap structures in the original circuit to configure the MUX logic. Additionally, N-MUX ensures high efficiency by selecting the false input from the direct neighbourhood of the true input. Experimental results on ISCAS’85 and ITC’99 benchmarks demonstrate that N-MUX is the most secure and reliable LL technique against SOTA ML-based attacks, achieving an 81% reduction in attack accuracy compared to existing MUX-based LL methods and delivering up to 480× greater efficiency.

Integrated Circuit (IC) verification is of paramount importance to the security of IC. The success of circuit verification largely depends on the correctness of the recovered circuit netlist from Scanning Electron Microscopic (SEM) images. Due to imperfections in imaging process and feature extraction process, the recovered circuit netlist usually contains connection errors. The corrections of these errors require tedious manual tracing of metal lines or are sometimes impossible due to the corrupt regions in SEM images. In this work, we perform error correction based on a connection heuristic in circuit. We propose MLConnect, a machine learning based connection prediction framework that captures the probabilities of gate connections in circuits. We further propose a post-processing technique to recover circuit connections based on gate connection probabilities and circuit rules. Our results show that the proposed MLConnect successfully recovered 80.87% of gate connections in erroneous circuits from ISCAS-85 benchmark suites. Our method can largely automate the process of circuit recovery.

Global distribution of the Integrated Circuit (IC) supply chain amplifies the importance of Hardware Assurance (HA), i.e., to ensure the integrity of manufactured IC. Standard cell recognition is a crucial step in HA, which is to identify the functionality of a standard cell based on its Scanning Electron Microscope (SEM) images. Conventionally, this is mostly done by human inspection, which is labor-intensive and error-prone. Current works on automating this process only work on the image domain and have sub-optimal performance due to the challenges incurred by the variation in the appearance of standard cells in the images. In this paper, we propose an automatic process for standard cell recognition, through conversion to a standardized graph representation and comparing the graph structure to identify the type of the standard cell. Our proposed method represents each unique circuit structure in a unique graph representation and thus enables a one-to-one matching to a known set of templates for functionality identification. Our experiments show that our proposed method can always recognize the standard cells correctly, even under the most challenaing scenario.