Demo Data from EDBT 2026 / reviewers in the wild / expert
Tzofnat Greenberg-Toledo
dblp:235/6323
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2024
0000-0001-6477-6113ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Hardware security and side channels · 50% Security and privacy of machine learning · 50% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 50% Emerging computing paradigms · 50% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
intellectual property protection |
0.8 | 1 | 2024 | TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Security and privacy of machine learning › model intellectual property protection
model weight protection |
0.8 | 1 | 2024 | TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Emerging computing paradigms
memristive computing |
0.8 | 1 | 2024 | TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Memory systems
non-volatile memory |
0.8 | 1 | 2024 | TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural Networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Methods — techniques the papers use, named apart from their topics
2-d permutation · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural NetworksabstractThe execution of deep neural network (DNN) algorithms suffers from significant bottlenecks due to the separation of the processing and memory units in traditional computer systems. Emerging memristive computing systems introduce an in situ approach that overcomes this bottleneck. The nonvolatility of memristive devices, however, may expose the DNN weights stored in memristive crossbars to potential theft attacks. Therefore, this article proposes a 2-D permutation-based protection (TDPP) method that thwarts such attacks. We first introduce the underlying concept that motivates the TDPP method: permuting both the rows and columns of the DNN weight matrices. This contrasts with previous methods, which focused solely on permuting a single dimension of the weight matrices, either the rows or columns. While it is possible for an adversary to access the matrix values, the original arrangement of rows and columns in the matrices remains concealed. As a result, the extracted DNN model from the accessed matrix values would fail to operate correctly. We consider two different memristive computing systems (designed for layer-by-layer and layer-parallel processing, respectively), and demonstrate the design of the TDPP method that could be embedded into the two systems. Finally, we present a security analysis. Our experiments demonstrate that TDPP can achieve comparable effectiveness to prior approaches, with a high level of security when appropriately parameterized. In addition, TDPP is more scalable than previous methods and results in reduced area and power overheads. The area and power are reduced by, respectively,$1218\times $and$2815\times $for the layer-by-layer system and by$178\times $and$203\times $for the layer-parallel system compared to prior works. Minhui Zou, Zhenhua Zhu 0002, Tzofnat Greenberg-Toledo, Orian Leitersdorf, Jiang Li 0012, Junlong Zhou, Yu Wang 0002, Nan Du 0004, Shahar Kvatinsky |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |