As CMOS technology continues to scale, the associated reduction in device reliability margins has made accurate reliability evaluation a critical component of digital circuit design. Traditional methods typically assess reliability based on the average behavior of multiple input vectors (MIVs), while neglecting the significant variation introduced by individual input vector (IIV). In practice, different IVs often exhibit heterogeneous reliability distributions, and in sequential circuits with temporal correlation, these differences may span several orders of magnitude. This paper proposes a probabilistic injection framework for reliability analysis that explicitly considers input correlation in a sequential circuit. The method enables both fine-grained evaluation for each IIV and global assessment across MIVs, thereby offering a comprehensive understanding of not only average circuit reliability but also reliability bounds under specific input conditions. Experimental results on ISCAS’89, ITC’99, IWLS’05 and reference benchmark circuits demonstrate that the proposed approach achieves higher accuracy and greater stability compared to traditional methods.

Area and reliability optimization have become the primary constraints in circuits logic synthesis. To address the increasing area and transient fault susceptibility in combinational circuits, we propose a high-dimensional genetic algorithm (HGA). HGA adopts an evolutionary scheme based on ternary tree, and uses adaptive crossover operator and flight operator to jump out of local optimum. Moreover, based on the HGA, we propose an area and reliability optimization method (AROM) for mixed polarity Reed-Muller logic circuits, which searches the best polarity with minimum area and soft error rate. The experimental results confirm that AROM can search for more desirable nondominated solutions in less time compared to existing optimization methods, and can be used as an effective electronic design automation tool for multi-objective optimization.

Hardware Trojans (HTs) pose a significant threat to the security of integrated circuits(ICs). Measuring the vulnerability of ICs to HT insertions is crucial for enhancing design security, thereby mitigating potential security risks. This paper proposes a novel vulnerability measurement method for ICs against HT insertions based on node co-activation analysis. The method first transforms the circuit structure into a graph representation, where nodes represent circuit interconnections, and edges represent circuit components, using graph learning (GL) techniques. Next, it calculates the logical probability distribution and logic flip probability for each circuit node using simulation methods. By combining an adaptive threshold filtering strategy, the method identifies suspicious nodes in the circuit using simulation methods combined with an adaptive threshold screening strategy to identify suspicious nodes in circuits. Subsequently, it computes the joint probabilities of pairs of suspicious nodes that simultaneously exhibit rare logic values based on simulation results. Finally, the vulnerability of the circuit to HT insertions is quantified by evaluating the co-activation between pairs of suspicious nodes. Experimental results demonstrate the effectiveness, efficiency, and generalization capability of the proposed method.

Accurate and efficient identification of reliability-critical paths (RCPs) not only facilitates fault localization and troubleshooting but also allows circuit designers to improve circuit reliability at a low cost. This article proposes a local and global adjacency probability matrix-based approach (LGAPM) to quickly and efficiently identify RCPs of combinational logic circuits. The approach reflects the criticality of the overall reliability of the circuit as well as the local criticality of gates in the path. In addition, we design a pruning-based method to accelerate RCP identification in large-scale circuits. The experimental results of the LGAPM on all 74 series circuits, ISCAS-85, and partial EPFL benchmark circuits show that the 74181 circuit with a minimum of 17 paths and the EPFL-remainder10 circuit with a maximum of 8.081 × 108paths take times of about 0.18s and 33931.04s, respectively. The average accuracy on small and medium-scale circuits is 94.24%, and the average stability on all-size circuits is 86.19%. Compared to the SAT-based method, hill-climbing algorithm, and random method, LGAPM’s metrics are superior and more appropriate for large-scale circuits. The overall circuit reliability can be improved from 0.7726 to 0.9238 on average by hardening a tiny number of gates in the identified the most RCPs and the average cost savings is 4.08 times over random hardening methods.

The identification of reliability-critical input vectors (RCIVs) is vital in the assessment and prediction of reliability boundaries for logic circuits. This article introduces an approach grounded in association rule analysis (ARA) to swiftly and efficiently identify RCIVs in both combinational and sequential circuits. The utilization of the ARA model for validating the circuit’s associated primary inputs enhances accuracy while simultaneously reducing the complexity of RCIVs identification. Orienting the generation of new samples with associated inputs expedites the identification process. Quantifying circuit complexity enables the adaptive assignment of algorithmic parameters to circuits of diverse sizes. The construction of input sets facilitates a precise evaluation of the reliability of individual input vectors in sequential circuits. Experimental results on benchmark circuits illustrate that this approach achieves a mean accuracy of 0.9952, with Monte Carlo (MC) method serving as the reference, for small and medium-sized circuits, and require only 20.71% of MC’s time overhead. The average coverage of 0.9884 surpasses the reference method by 1.8 times. The stability is 4.35 times higher with the random method on large scale circuits with 224,624 gates and 6,642 primary inputs. Circuit designers can swiftly ascertain the average reliability and reliability boundaries of a circuit by using this approach for RCIVs identification. By applying optimizations of the identified RCIVs to expedite convergence and mitigate fluctuations, the influence of these RCIVs can be minimized in reliability evaluation and testing.

The dependability of systems gains extensive attention as they are vulnerable to unexpected events, such as soft errors in circuits. Many works proposed to enhance the reliability of circuits at a low cost by hardening the reliability-critical gates (RCGs). However, it is challenging and necessary to determine the gates that need to be improved, especially for sequential circuits. Currently, methods used to locate RCGs for sequential circuits are struggling to balance the accuracy and computational overhead. This paper presents a method for locating RCGs of sequential circuits, the states of gates are aggregated into slices based on the time window graph model, then a probability-based calculation method is proposed for quantifying the criticality of gate reliability oriented to slices, finally, locating RCGs for sequential circuits which takes the accumulation of faults into consideration. Experiments on fifty ISCAS-89 and six ITC-99 benchmark circuits show that, on average, the accuracy of our method is 0.9417 of that of Monte Carlo (MC) method, and the speed and memory cost are 1725 times faster and 5.57 times lower than those of MC method. In addition, the proposed method is much faster and more accurate than stochastic method for large-scale circuits.

Accurate and effective localization of reliability-critical gates (RCGs) is one of the important prerequisites for low-cost circuit fault tolerance in the early stages of circuit design. This article introduces an accurate and effective approach for localizing RCGs in combinational logic blocks through a benchmarking technique. In the proposed approach, uniform non-Bernoulli sequences are used to produce a set of input vectors for driving circuits. A full-period linear congruential algorithm is employed to generate a sequence that provides the sampled order for the RCGs to be analyzed. This ensures that each gate in the circuit is treated as fairly as possible. To accelerate the localization process, an input-vector-based pruning technique combined with a counting method is also introduced to identify the specified number of RCGs. Then, the criticality of gate reliability for each RCG is measured through benchmarking. A clustering algorithm carries out the convergence checking for the proposed approach. The performance of the proposed approach was evaluated in terms of accuracy, stability, and time-space overhead by various simulations on 74-series circuits and ISCAS-85 benchmark circuits. The results show that its accuracy is close to that of the Monte Carlo model and its stability is better than that of other approximate methods. Moreover, compared with approximate methods, the time overhead of our approach is advantageous in the presence of similar memory overheads.