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Sreevatsa Anantharamu

dblp:236/0517 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2026
0009-0006-0414-2200ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
GPUs and heterogeneous computing · 52% High-performance computing · 26% Hardware accelerators and domain-specific architectures · 8%
Computer networks
1 paper
Datacenter networks · 100%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing
collective communication
1.012026
MSCCL++: Rethinking GPU Communication Abstractions for AI Inference · ASPLOS (2) 2026
GPUs and heterogeneous computing
GPU communication
1.012026
MSCCL++: Rethinking GPU Communication Abstractions for AI Inference · ASPLOS (2) 2026
Datacenter networks
RDMA
0.912025
SDR-RDMA: Software-Defined Reliability Architecture for Planetary Scale RDMA Communication · SC 2025
Hardware accelerators and domain-specific architectures › machine learning accelerator
inference accelerator
0.312026
MSCCL++: Rethinking GPU Communication Abstractions for AI Inference · ASPLOS (2) 2026
Distributed systems › distributed machine learning
distributed training
0.312025
SDR-RDMA: Software-Defined Reliability Architecture for Planetary Scale RDMA Communication · SC 2025
Cloud and datacenter computing › cloud networking
inter-datacenter network
0.312025
SDR-RDMA: Software-Defined Reliability Architecture for Planetary Scale RDMA Communication · SC 2025

Methods — techniques the papers use, named apart from their topics

selective repeat · 1.7erasure coding · 1.7low-level primitive interface · 1.0DSL for communication algorithms · 1.0
YearPublicationVenuePosition
2026 MSCCL++: Rethinking GPU Communication Abstractions for AI Inference
abstract
AI applications increasingly run on fast-evolving, heterogeneous hardware to maximize performance, but general-purpose libraries lag in supporting these features. Performance-minded programmers often build custom communication stacks that are fast but error-prone and non-portable. This paper introduces MSCCL++, a design methodology for developing high-performance, portable communication kernels. It provides (1) a low-level, performance-preserving primitive interface that exposes minimal hardware abstractions while hiding the complexities of synchronization and consistency, (2) a higher-level DSL for application developers to implement workload-specific communication algorithms, and (3) a library of efficient algorithms implementing the standard collective API, enabling adoption by users with minimal expertise. Compared to state-of-the-art baselines, MSCCL++ achieves geomean speedups of 1.7× (up to 5.4×) for collective communication and 1.2× (up to 1.38×) for AI inference workloads. MSCCL++ is in production of multiple AI services provided by Microsoft Azure, and has also been adopted by RCCL, the GPU collective communication library maintained by AMD. MSCCL++ is open source and available at https://github.com/microsoft/mscclpp. Our two years of experience with MSCCL++ suggests that its abstractions are robust, enabling support for new hardware features, such as multimem, within weeks of development.
Changho Hwang, Peng Cheng 0005, Roshan Dathathri, Abhinav Jangda, Saeed Maleki, Madan Musuvathi, Olli Saarikivi, Aashaka Shah, Ziyue Yang 0002, Binyang Li, Caio Rocha, Mahdieh Ghazimirsaeed, Sreevatsa Anantharamu
ASPLOS (2)14
2025 SDR-RDMA: Software-Defined Reliability Architecture for Planetary Scale RDMA Communication
abstract
RDMA is vital for efficient distributed training across datacenters, but millisecond-scale latencies complicate the design of its reliability layer. We show that depending on long-haul link characteristics, such as drop rate, distance and bandwidth, the widely used Selective Repeat algorithm can be inefficient, warranting alternatives like Erasure Coding. To enable such alternatives on existing hardware, we propose SDR-RDMA, a software-defined reliability stack for RDMA. Its core is a lightweight SDR SDK that extends standard point-to-point RDMA semantics — fundamental to AI networking stacks — with a receive buffer bitmap. SDR bitmap enables partial message completion to let applications implement custom reliability schemes tailored to specific deployments, while preserving zero-copy RDMA benefits. By offloading the SDR backend to NVIDIA’s Data Path Accelerator (DPA), we achieve line-rate performance, enabling efficient inter-datacenter communication and advancing reliability innovation for inter-datacenter training.
Mikhail Khalilov, Marcin Chrapek, Tiancheng Chen, Kenji Nakano, Nicola Mazzoletti, Peter-Jan Gootzen, Salvatore Di Girolamo, Rami Nudelman, Gil Bloch, Abdul Kabbani, Sreevatsa Anantharamu, Konstantin Taranov, Zhuolong Yu, Scott Moe, Mahmoud Elhaddad, Torsten Hoefler
SC13